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853S12AKI PDF预览

853S12AKI

更新时间: 2024-01-25 00:18:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
16页 396K
描述
Low Skew Clock Driver, 853S Series, 12 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32

853S12AKI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.33其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:853S输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N32JESD-609代码:e0
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:12
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:5 mm
Base Number Matches:1

853S12AKI 数据手册

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ICS853S12I  
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER  
PRELIMINARY  
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C  
Symbol Parameter  
fMAX Output Frequency  
tPD  
Test Conditions  
Minimum Typical Maximum Units  
3
GHz  
ps  
Propagation Delay; NOTE 1  
490  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter Section  
622MHz, Integration Range:  
12kHz – 20MHz  
tjit  
0.05  
ps  
tsk(o)  
tsk(pp)  
tR / tF  
odc  
Output Skew; NOTE 2, 4  
Part-to-Part Skew; NOTE 3, 4  
Output Rise/Fall Time  
Output Duty Cycle  
25  
90  
ps  
ps  
ps  
20ꢀ to 80ꢀ  
170  
50  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured  
at the differential cross points.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C  
Symbol Parameter  
fMAX Output Frequency  
tPD  
Test Conditions  
Minimum Typical Maximum Units  
3
GHz  
ps  
Propagation Delay; NOTE 1  
495  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter Section  
622MHz, Integration Range:  
12kHz – 20MHz  
tjit  
0.05  
ps  
tsk(o)  
tsk(pp)  
tR / tF  
odc  
Output Skew; NOTE 2, 4  
Part-to-Part Skew; NOTE 3, 4  
Output Rise/Fall Time  
Output Duty Cycle  
25  
90  
ps  
ps  
ps  
20ꢀ to 80ꢀ  
165  
50  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured  
at the differential cross points.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
IDT/ ICSLVPECL FANOUT BUFFER  
4
ICS853S12AKI REV. A MARCH 29, 2007  

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