853S111AI DATA SHEET
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, SSTL, CML and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
C1
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
VBB
C2
Zo = 50Ω
nPCLK
nPCLK
LVPECL
Input
LVPECL
Input
LVPECL
R5 R6
100Ω - 200Ω 100Ω - 200Ω
R1
50Ω
R2
50Ω
R1
84Ω
R2
84Ω
Figure 2A. PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver
Figure 2B. PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
2.5V
3.3V
3.3V
3.3V
Zo = 50Ω
2.5V
C1
C2
PCLK
VBB
R5
100Ω
PCLK
nPCLK
Zo = 50Ω
LVPECL
Input
LVDS
nPCLK
R1
1k
R2
1k
LVPECL
Input
SSTL
C3
0.1µF
Figure 2C. PCLK/nPCLK Input Driven by an SSTL Driver
Figure 2D. PCLK/nPCLK Input Driven by
a 3.3V LVDS Driver
3.3V
3.3V
3.3V
Zo = 50Ω
3.3V
3.3V
R1
50Ω
R2
50Ω
PCLK
Zo = 50Ω
Zo = 50Ω
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
nPCLK
LVPECL
Input
CML Built-In Pullup
LVPECL
Input
CML
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver
Figure 2F. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Rev A 6/30/15
10
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT
BUFFER