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853S111BYILFT PDF预览

853S111BYILFT

更新时间: 2024-02-24 13:12:49
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
25页 451K
描述
Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL Fanout Buffer

853S111BYILFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:PTQFP
包装说明:TQFP-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.64
Samacsys Description:TQFP 7 X 7 X1.0 MM- EXPOSED PAD系列:853S
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTQFP
封装等效代码:TQFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE峰值回流温度(摄氏度):260
电源:+-2.5/+-3.3 VProp。Delay @ Nom-Sup:0.645 ns
传播延迟(tpd):0.61 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:2500 MHzBase Number Matches:1

853S111BYILFT 数据手册

 浏览型号853S111BYILFT的Datasheet PDF文件第2页浏览型号853S111BYILFT的Datasheet PDF文件第3页浏览型号853S111BYILFT的Datasheet PDF文件第4页浏览型号853S111BYILFT的Datasheet PDF文件第5页浏览型号853S111BYILFT的Datasheet PDF文件第6页浏览型号853S111BYILFT的Datasheet PDF文件第7页 
Low Skew, 1-to-10, Differential-to-2.5V,  
3.3V LVPECL/ECL Fanout Buffer  
853S111B  
General Description  
Features  
The 853S111B is a low skew, high performance 1-to-10  
Ten differential 2.5V, 3.3V LVPECL/ECL outputs  
Two selectable differential input pairs  
Differential-to-2.5V/ 3.3V LVPECL/ECL Fanout Buffer. The  
853S111B is characterized to operate from either a 2.5V or a 3.3V  
power supply. Guaranteed output and part-to-part skew  
characteristics make the 853S111B ideal for those clock distribution  
applications demanding well defined performance and repeatability.  
PCLKx, nPCLKx pairs can accept the following  
differential input levels: LVPECL, LVDS, SSTL, CML  
Maximum output frequency: 2.5GHz  
Translates any single-ended input signal to 3.3V LVPECL levels  
with resistor bias on nPCLK input  
Output skew: 50ps (maximum)  
Part-to-part skew: 150ps (maximum)  
Propagation delay: 645ps (maximum)  
Additive Phase Jitter, RMS: 0.03ps (typical)  
LVPECL mode operating voltage supply range:  
Pin Assignments  
VCC = 2.375V to 3.8V, VEE = 0V  
ECL mode operating voltage supply range:  
VCC = 0V, VEE = -3.8V to -2.375V  
24 23 22 21 20 19 18 17  
25  
VCCO  
VCCO  
16  
15  
-40°C to 85°C ambient operating temperature  
Available lead-free (RoHS 6) packaging  
26  
nQ2  
Q2  
Q7  
853S111B  
nQ7  
Q8  
27 32-Lead TQFP, E-Pad 14  
28  
nQ1  
Q1  
13  
7mm x 7mm x 1mm  
nQ8  
29  
30  
31  
32  
12  
11  
10  
9
Block Diagram  
package body  
Y Package  
Top View  
nQ0  
Q0  
Q9  
Pulldown  
PCLK0  
0
1
Pullup/Pulldown  
nQ9  
VCCO  
Q0  
nPCLK0  
VCCO  
nQ0  
Pulldown  
PCLK1  
1
2
3
4
5
6
7
8
Pullup/Pulldown  
nPCLK1  
Q1  
nQ1  
Pulldown  
CLK_SEL  
VBB  
Q2  
nQ2  
nQ3  
nQ3  
24 23 22 21 20 19 18 17  
Q4  
25  
26  
27  
VCCO  
VCCO  
16  
15  
14  
13  
12  
nQ4  
Q5  
nQ2  
Q2  
Q7  
853S111B  
nQ7  
Q8  
nQ5  
32-Lead VFQFN  
28 5mm x 5mm x 0.925mm  
nQ1  
Q1  
Q6  
nQ8  
29  
package body  
K Package  
nQ6  
nQ0  
Q0  
30  
Q9  
11  
10  
9
Q7  
Top View  
31  
nQ9  
VCCO  
nQ7  
VCCO  
32  
1
2
3
4
5
6
7
8
nQ8  
nQ8  
Q9  
nQ9  
©2016 Integrated Device Technology, Inc.  
1
Revision F, January 14, 2016  

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