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853S111AYILF PDF预览

853S111AYILF

更新时间: 2024-02-22 01:09:46
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
20页 298K
描述
Differential-to-LVPECL/ECL Fanout Buffer

853S111AYILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:2.26
系列:S输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:+-2.5/+-3.3 V
Prop。Delay @ Nom-Sup:0.8 ns传播延迟(tpd):0.745 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.55 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:2500 MHz
Base Number Matches:1

853S111AYILF 数据手册

 浏览型号853S111AYILF的Datasheet PDF文件第7页浏览型号853S111AYILF的Datasheet PDF文件第8页浏览型号853S111AYILF的Datasheet PDF文件第9页浏览型号853S111AYILF的Datasheet PDF文件第11页浏览型号853S111AYILF的Datasheet PDF文件第12页浏览型号853S111AYILF的Datasheet PDF文件第13页 
853S111AI DATA SHEET  
LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, SSTL, CML and other  
differential signals. Both VSWING and VOH must meet the VPP and  
VCMR input requirements. Figures 2A to 2F show interface examples  
for the PCLK/nPCLK input driven by the most common driver types.  
The input interfaces suggested here are examples only. If the driver  
is from another vendor, use their termination recommendation.  
Please consult with the vendor of the driver component to confirm the  
driver termination requirements.  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
R3  
125  
R4  
125Ω  
C1  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
3.3V LVPECL  
PCLK  
PCLK  
VBB  
C2  
Zo = 50Ω  
nPCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
Input  
LVPECL  
R5 R6  
100- 200100- 200Ω  
R1  
50Ω  
R2  
50Ω  
R1  
84Ω  
R2  
84Ω  
Figure 2A. PCLK/nPCLK Input Driven by  
a 3.3V LVPECL Driver  
Figure 2B. PCLK/nPCLK Input Driven by  
a 3.3V LVPECL Driver with AC Couple  
2.5V  
3.3V  
3.3V  
3.3V  
Zo = 50Ω  
2.5V  
C1  
C2  
PCLK  
VBB  
R5  
100Ω  
PCLK  
nPCLK  
Zo = 50Ω  
LVPECL  
Input  
LVDS  
nPCLK  
R1  
1k  
R2  
1k  
LVPECL  
Input  
SSTL  
C3  
0.1µF  
Figure 2C. PCLK/nPCLK Input Driven by an SSTL Driver  
Figure 2D. PCLK/nPCLK Input Driven by  
a 3.3V LVDS Driver  
3.3V  
3.3V  
3.3V  
Zo = 50  
3.3V  
3.3V  
R1  
50Ω  
R2  
50Ω  
PCLK  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
R1  
100Ω  
nPCLK  
Zo = 50Ω  
nPCLK  
LVPECL  
Input  
CML Built-In Pullup  
LVPECL  
Input  
CML  
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver  
Figure 2F. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
Rev A 6/30/15  
10  
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT  
BUFFER  

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