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85314AG-01T PDF预览

85314AG-01T

更新时间: 2024-11-13 20:53:19
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 338K
描述
Low Skew Clock Driver, PDSO20

85314AG-01T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.5
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:2.1 ns认证状态:Not Qualified
子类别:Clock Drivers标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30Base Number Matches:1

85314AG-01T 数据手册

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DATA SHEET  
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL  
ICS85314-01  
FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS85314-01 is a low skew, high performance 5 differential 2.5V/3.3V LVPECL outputs  
1-to-5 Differential-to-3.3V LVPECL fanout buffer  
Selectable differential CLK0, nCLK0 or LVCMOS inputs  
HiPerClockS™  
and a member of the HiPerClockS™ family of  
High Performance Clock Solutions from ICS.  
The ICS85314-01 has two selectable clock inputs.  
CLK0, nCLK0 pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
The CLK0, nCLK0 pair can accept most standard differential  
input levels. The single-ended CLK1 can accept LVCMOS or  
LVTTL input levels. The clock enable is internally synchronized  
to eliminate runt clock pulses on the outputs during asynchro-  
nous assertion/deassertion of the clock enable pin.  
CLK1 can accept the following input levels:  
LVCMOS or LVTTL  
Maximum output frequency: 650MHz  
Translates any single-ended input signal to 3.3V LVPECL  
levels with resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics make  
the ICS85314-01 ideal for those applications demanding well  
defined performance and repeatability.  
Output skew: 50ps (maximum)  
Part-to-part skew: 400ps (maximum)  
Propagation delay: CLK0, nCLK0 - 2.1ns (maximum)  
CLK1 - 2.1ns (maximum)  
LVPECL mode operating voltage supply range:  
VCC = 2.375V to 3.8V, VEE = 0V  
-40°C to 85°C ambient operating temperature  
Compatible to part number MC100LVEL14  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
Q1  
nQ1  
Q2  
nQ2  
Q3  
nQ3  
Q4  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
nCLK_EN  
VCC  
D
nCLK_EN  
Q
LE  
CLK0  
nCLK0  
nc  
0
Q0  
nQ0  
CLK1  
CLK0  
nCLK0  
nc  
1
CLK1  
Q1  
nQ1  
CLK_SEL  
VEE  
CLK_SEL  
nQ4  
Q2  
nQ2  
ICS85314-01  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.92mm Package Body  
G Package  
Q3  
nQ3  
Q4  
nQ4  
Top View  
ICS85314-01  
20-Lead SOIC  
7.5mm x 12.8mm x 2.3mm Package Body  
M Package  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
IDT™ / ICS™ LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
ICS85314-01  
1

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