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843S1333DGLF PDF预览

843S1333DGLF

更新时间: 2024-11-05 01:14:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
15页 336K
描述
Crystal-to-3.3V LVPECL Clock Synthesizer

843S1333DGLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.4 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:1333.33 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:20 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:80 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

843S1333DGLF 数据手册

 浏览型号843S1333DGLF的Datasheet PDF文件第2页浏览型号843S1333DGLF的Datasheet PDF文件第3页浏览型号843S1333DGLF的Datasheet PDF文件第4页浏览型号843S1333DGLF的Datasheet PDF文件第5页浏览型号843S1333DGLF的Datasheet PDF文件第6页浏览型号843S1333DGLF的Datasheet PDF文件第7页 
Crystal-to-3.3V LVPECL Clock  
Synthesizer  
843S1333D  
Data Sheet  
General Description  
Features  
The 843S1333D is a high frequency clock generator. The  
843S1333D uses an external 20MHz crystal to synthesize  
1333.33MHz. The 843S1333D has excellent cycle-to-cycle and  
RMS period jitter performance.  
One differential LVPECL output  
Crystal oscillator interface designed for 18pF, 20MHz parallel  
resonant crystal  
Cycle-to-Cycle Jitter: 14ps (maximum)  
Period Jitter, RMS: 2.6ps (maximum)  
Output Duty Cycle: 48 – 52%  
The 843S1333D operates at 3.3V operating supply and is available  
in a fully RoHS compliant 8-lead TSSOP package.  
Full 3.3V supply mode  
0°C to 70°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Table 1. Frequency Table  
Crystal Frequency (MHz)  
Multiplier Value  
Output Frequency (MHz)  
1333.33  
20  
66.67  
Pin Assignment  
Block Diagram  
Pullup  
OE  
VCCA  
1
8
7
6
5
VCC  
Q
20MHz  
EE  
V
2
XTAL_IN  
Q
XTAL_OUT  
3
XTAL_IN  
nQ  
OE  
OSC  
PLL Multiplier  
(x66.67)  
nQ  
4
XTAL_OUT  
843S1333D  
8 Lead TSSOP  
4.40mm x 3.0mm x 0.925mm package body  
G Package  
Top View  
©2015 Integrated Device Technology, Inc  
1
Revision A December 2, 2015  

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