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843256IBGILF PDF预览

843256IBGILF

更新时间: 2024-11-03 19:58:15
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
16页 1620K
描述
PLL/Frequency Synthesis Circuit, PDSO24

843256IBGILF 技术参数

是否Rohs认证: 符合生命周期:End Of Life
包装说明:TSSOP, TSSOP24,.25Reach Compliance Code:compliant
风险等级:5.79JESD-30 代码:R-PDSO-G24
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
子类别:PLL or Frequency Synthesis Circuits标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

843256IBGILF 数据手册

 浏览型号843256IBGILF的Datasheet PDF文件第2页浏览型号843256IBGILF的Datasheet PDF文件第3页浏览型号843256IBGILF的Datasheet PDF文件第4页浏览型号843256IBGILF的Datasheet PDF文件第5页浏览型号843256IBGILF的Datasheet PDF文件第6页浏览型号843256IBGILF的Datasheet PDF文件第7页 
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY  
SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER  
ICS843256I  
GENERAL DESCRIPTION  
FEATURES  
The ICS843256I is a Crystal-to-3.3V LVPECL Clock  
• Six 3.3V differential LVPECL output pairs  
ICS  
HiPerClockS™  
Synthesizer/Fanout Buffer designed for Fibre  
Channel and Gigabit Ethernet applications and is  
a member of the HiperClockS™ family of High  
Performance Clock Solutions from IDT. The output  
• Output frequency range: 62.5MHz to 625MHz  
Crystal input frequency range: 15.625MHz to 25.5MHz  
RMS phase jitter at 156.25MHz, using a 25MHz crystal  
(1.875MHz to 20MHz): 0.41ps (typical) @ 3.3V  
frequency can be set using the frequency select pins and a  
25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal  
for SONET. The low phase noise characteristics of the  
ICS843256I make it an ideal clock for these demanding  
applications.  
Operating supply modes:  
Core/Output  
3.3V/3.3V  
3.3V/2.5V  
• -40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
SELECT FUNCTION TABLE  
Inputs  
Function  
FB_SEL N_SEL1 N_SEL0 M Divide N Divide  
M/N  
25  
12.5  
6.25  
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25  
25  
25  
25  
32  
32  
32  
32  
1
2
4
5
1
2
4
8
32  
16  
8
4
Q0  
PIN ASSIGNMENT  
BLOCK DIAGRAM  
nQ0  
VCCO  
VCCO  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Q3  
Pullup  
PLL_BYPASS  
2
3
4
5
6
7
8
9
nQ3  
Q4  
nQ4  
Q5  
nQ5  
N_SEL1  
VEE  
Q1  
nQ2  
Q2  
nQ1  
Q1  
nQ0  
Q0  
1
nQ1  
Q2  
N
XTAL_IN  
Output  
Divider  
PLL  
OSC  
0
XTAL_OUT  
PLL_BYPASS  
VCCA  
VEE  
nQ2  
Q3  
10  
11  
12  
N_SEL0  
XTAL_OUT  
XTAL_IN  
VCC  
FB_SEL  
M
Feedback  
Divider  
nQ3  
Q4  
24-Lead TSSOP, E-Pad  
4.40mm x 7.8mm x 0.92mm  
body package  
Pulldown  
FB_SEL  
Pullup  
G Package  
Top View  
N_SEL1  
nQ4  
Q5  
Pullup  
N_SEL0  
nQ5  
IDT/ ICS3.3V LVPECL FREQUENCY SYNTHESIZER  
1
ICS843256BGI REV. A OCTOBER 23, 2008  

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