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813078BYILF

更新时间: 2024-11-11 06:32:43
品牌 Logo 应用领域
艾迪悌 - IDT 石英晶振压控振荡器无线
页数 文件大小 规格书
26页 981K
描述
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT

813078BYILF 数据手册

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FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR  
FOR WIRELESS INFRASTRUCTURE EQUIPMENT  
ICS813078I  
General Description  
Features  
The ICS813078I is a member of the HiperClocks  
Nine outputs, organized in three independent output banks with  
differential LVPECL and single-ended outputs  
S
IC  
family of high performance clock solutions from IDT.  
The ICS813078I a PLL based synchronous clock  
solution that is optimized for wireless infrastructure  
equipment where frequency translation and jitter  
HiPerClockS™  
One differential input clock can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL  
One single-ended clock input  
attenuation is needed.  
Frequency generation optimized for wireless infrastructure  
Attenuates the phase jitter of the input clock signal by using  
The device contains two internal PLL stages that are cascaded in  
series. The first PLL stage attenuates the reference clock jitter by  
using an internal or external VCXO circuit. The internal VCXO  
requires the connection of an external inexpensive pullable crystal  
(XTAL) to the ICS813078I. This first PLL stage (VCXO PLL) uses  
external passive loop filter components which are used to optimize  
the PLL loop bandwidth and damping characteristics for the given  
application. The output of the first stage VCXO PLL is a stable and  
jitter-tolerant 30.72MHz reference input for the second PLL stage.  
The second PLL stage provides frequency translation by  
multiplying the output of the first stage up to 491.52MHz or  
614.4MHz. The low phase noise characteristics of the VCXO-PLL  
clock signal is maintained by the internal FemtoClock™PLL, which  
requires no external components or complex programming. Two  
independently configurable frequency dividers translate the  
internal VCO signal to the desired output frequencies. All  
low-cost pullable fundamental mode crystal (XTAL)  
Internal Femtoclock frequency multiplier stage eliminates the  
need for an expensive external high frequency VCXO  
LVCMOS levels for all control I/O  
RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal  
(12kHz to 20MHz): 1.1ps rms (typical)  
RMS phase jitter @ 61.44MHz, using a 30.72MHz crystal  
(12kHz to 20MHz): 0.97ps rms (typical)  
VCXO PLL bandwidth can be optimized for jitter attenuation and  
reference frequency tracking using external loop filter  
components  
PLL fast-lock control  
PLL lock detect output  
Absolute pull range is +/-50 ppm  
Full 3.3V supply voltage  
frequency translation ratios are set by device configuration pins.  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Supported input reference clock frequencies:  
10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz,  
61.44MHz, and 122.88MHz  
Supported output clock frequencies:  
30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz,  
153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz  
Pin Assignment  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
LF1  
LF0  
1
2
3
4
5
nc  
nc  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
ISET  
nc  
VCCO  
nQA0  
QA0  
FLM  
VCC  
VCC  
6
7
8
VEE  
nQA1  
64-Lead TQFP, E-Pad  
10mm x 10mm x 1mm  
package body  
CLK1  
REF_SEL  
nMR  
QA1  
9
VCCO  
nQA2  
Y Package  
10  
11  
12  
13  
14  
CLK0  
38 QA2  
VCC  
nCLK0  
VEE  
37  
VEE  
nQB0  
36  
35  
NA1  
NA0  
NB1  
15  
16  
QB0  
VCCO  
34  
33  
17 18 19 20 21  
23 24 25 26 27 28 29 30 31 32  
22  
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR  
1
ICS813078BYI REV. A OCTOBER 6, 2008  

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