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79RV4700-80GH PDF预览

79RV4700-80GH

更新时间： 2024-11-11 06:32:19
品牌 Logo 应用领域
艾迪悌 - IDT 微处理器
页数 文件大小 规格书
25页 780K
描述
64-Bit RISC Microprocessor

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79RV4700-80GH 数据手册

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IDT79R4700  
64-Bit RISC Microprocessor  
◆
Available at 80-200MHz, with mode bit dependent output  
clock frequencies  
Features  
◆
True 64-bit microprocessor  
◆
◆
64GB physical address space  
–
–
–
–
64-bit integer operations  
64-bit floating-point operations  
64-bit registers  
Processor family for a wide variety of embedded  
applications  
64-bit virtual address space  
–
–
–
LAN switches  
Routers  
Color printers  
◆
High-performance microprocessor  
–
260 Dhrystone MIPS at 200MHz  
100 peak MFLOP/s at 200MHz  
Two-way set associative caches  
Simple 5-stage pipeline  
–
–
–
Description  
◆
The IDT79R4700 64-bit RISC Microprocessor is both software and  
pin-compatible with the R4XXX processor family. With 64-bit processing  
capabilities, the R4700 provides more computational power and data  
movement bandwidth than is delivered to typical embedded systems by  
32-bit processors.  
High level of integration  
–
64-bit, 200 MHz integer CPU  
64-bit floating-point unit  
16KB instruction cache  
16KB data cache  
Flexible MMU with large, fully associative TLB  
–
–
–
–
The R4700 is upwardly software compatible with the IDT79R3000™  
◆
Low-power operation  
™
™
microprocessor family, including the IDTRISController 79R3051 ,  
–
3.3V power supply, for the “RV” part  
5V power supply, for the “R” part  
Dynamic power management  
™
™
™
™
™
–
–
–
R3052 , R3041 , R3081 as well as the R4640 , R4650 , RC64474/  
™
™
475 and R5000 . An array of development tools facilitates rapid  
development of R4700-based systems, allowing a variety of customers  
access to the MIPS Open Architecture philosophy.  
Standby mode reduces internal power  
◆
◆
Fully software & pin-compatible with 40XX Processor Family  
Available in 179-pin PGA or 208-pin QFP  
Block Diagram  
Data Tag A  
Data Set A  
Instruction Set A  
DTLB Physical  
Data Tag B  
Store Buffer  
SysAD  
Instruction Select  
Write Buffer  
Read Buffer  
Address Buffer  
Instruction Tag A  
ITLB Physical  
Instruction Register  
Data Set B  
DBus  
Instruction Set B  
Instruction Tag B  
IBus  
Control  
AuxTag  
Tag  
Load Aligner  
Floating-point  
Register File  
Joint TLB  
Integer Register File  
Integer/Address Adder  
Data TLB Virtual  
Shifter/Store Aligner  
Logic Unit  
Unpacker/Packer  
Floating-point  
Add/Sub/Cvt/Div/Sqrt  
Integer Divide  
Coprocessor 0  
DVA  
PC Incrementer  
Floating-point/Integer  
Multiply  
System/Memory  
Control  
Branch Adder  
Instruction TLB Virtual  
Program Counter  
IVA  
Phase Lock Loop, Clocks  
The IDT logo is a trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Inte-  
grated Device Technology, Inc.  
1 of 25  
December 5, 2008  
DSC 9096  
© 2008 Integrated Device Technology, Inc.  
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