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79RV5000200BS272I PDF预览

79RV5000200BS272I

更新时间： 2024-11-11 19:06:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路
页数 文件大小 规格书
15页 589K
描述
RISC Microprocessor, 64-Bit, 200MHz, PBGA272, SBGA-272

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79RV5000200BS272I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：272
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.87
地址总线宽度：64位大小：64
边界扫描：YES最大时钟频率：100 MHz
外部数据总线宽度：64格式：FLOATING POINT
集成缓存：YESJESD-30 代码：S-PBGA-B272
JESD-609代码：e0低功率模式：YES
端子数量：272最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
认证状态：Not Qualified速度：200 MHz
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
uPs/uCs/外围集成电路类型：MICROPROCESSOR, RISCBase Number Matches：1

79RV5000200BS272I 数据手册

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79RC5000  
MULTI-ISSUE  
64-BIT MICROPROCESSOR  
◆
Large, efficient on-chip caches  
Features  
–
–
–
32KB Instruction Cache, 32KB Data Cache  
2-set associative in each cach  
Virtually indexed and physically tagged to minimize cache  
flushes  
◆
Dual issue super-scalar execution core  
–
–
250 MHz frequency  
Dual issue floating-point ALU operations with other instruction  
classes  
–
–
–
Write-back and write-through selectable on a per page basis  
Critical word first cache miss processing  
Supports back-to-back loads and stores in any combination at  
full pipeline rate  
–
Traditional 5-stage pipeline, minimizes load and branch laten-  
cies  
◆
◆
Single-cycle repeat rate for most floating point ALU  
operations  
◆
High-performance memory system  
High level of performance for a variety of applications  
–
Large primary caches integrated on-chip  
Secondary cache control interface on-chip  
High-frequency 64-bit bus interface runs up to 125MHz  
Aggregate bandwidth of on-chip caches, system interface of  
5.6GB/s  
–
High-performance 64-bit integer unit achieves 330 dhrystone  
MIPS (dhrystone 2.1)  
–
–
–
–
Ultra high-performance floating-point accelerator, directly  
implementing single- and double-precision operations  
achieves 500mflops  
–
High-performance write protocols for graphics and data  
communications  
–
–
Extremely large on-chip primary cache  
On-chip secondary cache controller  
◆
Compatible with a variety of operating systems  
◆
MIPS-IV 64-bit ISA for improved computation  
–
–
Windows™ CE  
Numerous MIPS-compatible real-time operating systems  
–
Compound floating-point operations for 3D graphics and  
floating-point DSP  
◆
◆
Uses input system clock, with processor pipeline clock  
multiplied by a factor of 2-8  
–
Conditional move operations  
◆
◆
Large on-chip TLB  
Industrial and commercial temperature range  
Active power management, including use of WAIT operation  
Block Diagram  
Phase Lock Loop  
Data Tag A  
Instruction Set A  
Instruction Select  
Data Set A  
Store Buffer  
DTLB Physical  
SysAD  
Integer Instruction Register  
FP Instruction Register  
Address Buffer  
Instruction Tag A  
ITLB Physical  
Write Buffer  
Read Buffer  
Data Set B  
DBus  
Instruction Set B  
IntIBus  
Instruction Tag B  
FPIBus  
Control  
AuxTag  
Joint TLB  
Tag  
Load Aligner  
Floating Point Register File  
Unpacker/Packer  
Integer Register File  
Integer/Address Adder  
Coprocessor 0  
Data TLB Virtual  
DVA  
System/Memory  
Control  
Floating Point  
MAdd,Add,Sub, Cvt  
Div, SqRt  
Shifter/Store Aligner  
IVA  
PC Incrementer  
Branch Adder  
Logic Unit  
ABus  
Instruction TLB Virtual  
Program Counter  
Integer Multiply, Divide  
The IDT logo is a trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Inte-  
grated Device Technology, Inc.  
1 of 15  
April 10, 2001  
DSC 5719  
© 2001 Integrated Device Technology, Inc.  
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