78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
interface with the line media. Only an external
transient protector and a couple of EMI suppression
inductors are required with the transformer. Note
the transformer requires a coupling capacitor on the
line side.
FUNCTIONAL DESCRIPTION
GENERAL
Supply Voltage
The 78Q2132 can operate from either a single 3.3V
The 78Q2132 conforms to the required envelope for
transmission bursts on the line. See Figure 6 for the
detail of a single pulse burst signal.
(± 0.3V) or 5.0V (± 0.5V) power supply. The chip
automatically adapts to the supply voltage used. No
pin configuration is required.
The output is fed to a bandpass filter to reduce out-of-
band components. When not transmitting the transmit
circuitry is put into a mode that rejects common-mode
signals appearing at the receiver input.
Power Management
Chip power-down is activated by setting the PWRDN
bit in the MII register (MR0.11) or pulling high the
PWRDN pin. When the chip is in power-down
mode, all on-chip circuitry is shut off, and the device
consumes minimum power. While in power-down
state, the 78Q2132 still responds to the
management transactions.
HomePNA Receive
The 78Q2132 receives the encoded digital signal
through the same 1:1 transformer used for
transmission. The signal is internally filtered and
compared to an adjusted noise threshold prior to
being decoded.
From the resulting signal and
Analog Biasing
internal time reference a value is assigned to the
time interval. The value is RLL25 decoded and the
bit-stream is presented to the serial to parallel
converter. The parallel data from the converter is
then aligned and mapped as a 4 bit data for the MII
as outlined in Table 24-1 in Clause 24 of IEEE-802.3
or sent to the serial GSPI interface.
The 78Q2132 uses the onchip bandgap and an
external resistor to generate accurate bias voltages
and currents for the circuitry.
Clock Input
The 78Q2132 can use the on-chip crystal oscillator. In
this mode a 25MHz crystal is connected between the
XTAL_IN and XTAL_OUT pins. Alternatively, an
externally generated 25MHz clock can be connected
to the XTAL_IN pin. In conjunction with the oscillator
the device uses a PLLOSC to generate 60MHz which
is divided down by 3 to create 20MHz. It is further
divided for use by various functions on the chip. The
HomePNA section uses the time unit, TIC defined as
60MHz/7 (approx. 116.6ns).
The receive channel consists of
a
prefilter,
AGC/main filter, FWR, LPF and comparator with
adjustable level. Following the prefilter is a 2-level
AGC that compresses the dynamic range
requirements of the signal prior to going through the
main HomePNA receive filter.
Natural Loopback
When the 78Q2132 is transmitting on the twisted
pair media, data on the TXD pins is looped back
onto the RXD pins. The natural loopback function
can be disabled through register bit MR16.10.
HOMEPNA OPERATION
HomePNA Transmit
REFERENCE PACKET FRAMING AND
SEQUENCE
The 78Q2132 contains all of the necessary pulse
waveform circuitry to convert the transmit signaling
from a MAC to a HomePNA compliant data-stream.
The conversion is from either a 4bit parallel data
word via the MII interface or the serial data-stream
from GPSI interface to a serial data stream to a
RLL25 encoded set of 3 to 6bits. The value created,
between 0 and 24, is used to modulate the time, in
TIC increments, between pulse bursts. The pulse
bursts are filtered to bandlimit the signal passed to
the line driver, and to the line for transmission. The
integrated envelop-shaper reduces out-of-band
The frame passed between the MAC and 1M8 PHY
on TX-DATA and RX-DATA conforms to the 802.3
Ethernet MAC frame. When
a
pulse begins
transmission, the previous Symbol interval ends and
a new one immediately begins.
The Run Length Limit (RLL25) code was developed
for the 1M8 PHY. It produces both the highest bit
rate for a given value of Inter Symbol Blanking
Interval (ISBI) and Time Interval Clock (TIC) size. In
a manner similar to run length limited disk coding,
RLL25 encodes data bits in groups of varying sizes,
energy to reduce interference.
The line driver
requires an external 1:1 isolation transformer to
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