Datasheet > 78Q2132

78Q2132

更新时间： 2022-11-24 21:43:56

品牌	Logo	应用领域
东电化 - TDK		以太网
页数	文件大小	规格书
36页	173K
描述
1/10BASE-T HomePNA/Ethernet Transceiver

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78Q2132 数据手册

78Q2132

1/10BASE-TX

HomePNA/Ethernet Transceiver

MII (continued)

80-PIN 64-PIN TYPE

DESCRIPTION

MDC

MANAGEMENT DATA CLOCK: MDC is the clock used for

transferring data via the MDIO pin.

MDIO

I/O

MANAGEMENT DATA INPUT/OUTPUT: MDIO is

bi-

directional port used to access management registers within the

78Q2132. This pin requires an external pull-up resistor as

specified in IEEE-802.3.

PHYAD[4:0]

14-18

12-16

PHY ADDRESS: Allows 31 configurable PHY addresses. The

78Q2132 always responds to data transactions via the MII

interface when the PHYAD bits are all zero independent of the

logic levels of the PHYAD pins.

CONTROL AND STATUS

NAME

80-PIN 64-PIN

TYPE

DESCRIPTION

RST

RESET: When pulled low the pin resets the chip. There are 3

other ways to reset the chip:

through the internal power-on-reset (activated when

the chip is being powered up)

ii)

through the MII register bit MR 0.15

upon exiting power-down mode

iii)

Refer to the Reset Modes section for more details.

PWRDN

ISO

POWER-DOWN: The 2132 may be placed in a low power

consumption state by setting this signal to logic high. While in

power-down state, the 2132 still responds to management

transactions. The same power-down state can also be achieved

through the PWRDN bit in the MII register MR0.11.

N/A

ISOLATE: When set to logic one, the 2132 will present a high

impedance on its MII output pins. This allows for multiple PHYs to be

attached to the same MII interface. When the 2132 is isolated, it still

responds to management transactions. The same high impedance

state can also be achieved through the ISO bit in the MII register

MR0.10. This pin also sets the default of the ISO bit.

ISODEF

ANEGA

N/A

ISOLATE DEFAULT: This pin determines the power-up/reset

default of the ISO bit, MR0.10. If it is connected to VDD, ISO

bit will have a default value of 1. If it is connected to GND, ISO

bit will have a default value of 0.

AUTO-NEGOTIATION ABILITY: Strapped to logic high to allow

auto-negotiation function. When strapped to logic low, auto-

negotiation logic is disabled and manual technology selection

is done through TECH[2:0]. This pin is reflected as ANEGA bit

MR1.3.

1...4 5 678 9 10...36

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