78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
Carrier Sense, CRS, is asserted high whenever a
non-idle condition exists on either the receiver or the
transmitter. Typically, GPSI MACs will ignore CRS
during transmit modes.
ADDITIONAL FEATURES
LED Indicators
There are eight LED pins that can be used to
indicate various states of operation of the 2132.
There are LED pins that indicate when the 2132 is
either transmitting LEDTX or receiving LEDRX, one
that signals a collision event LEDCOL, two more that
reflect the data rate LED1 and LED10. LFD_SPD
reflects full duplex mode of operation when in 802.3
mode and transmit speed when in HomePNA mode.
LEDL indicates the link is up in either mode. The
LEDPWR pin indicates the power level of the
HomePNA port.
The Collision signal, CLSN, indicates a collision has
been detected by the 2132 on the wiring network.
MII/GPSI Selection
The MII on the 78Q2132 is internally connected to
the transmit and receive paths for either the 1M8
HomePNA or the 10BASE-T interface as described
in Clause 22 of the IEEE 802.3 standard. The
MII_EN pin selects the choice of interface or MII
Enable bit MR16.1. If the HomePNA port is enabled
the MII_EN pin or MII_Enable bit can select either
the MII or GPSI Interface. If the device is in
10BASE-T operation both the MII_EN pin and MII
Enable bit will have no effect on the selection
between MII and GPSI.
General Purpose I/O Interface
The 78Q2132 has a two pin, bi-directional, general
purpose interface that can be used for external
control or to monitor external signals. The direction
of these pins and the data that is either driven or
read from these pins is configured via bits MR16.9:6
as detailed in the Vendor Specific Register
description in MR16.
Station Management Interface
The station management interface consists of
circuitry which implements the serial protocol as
described in Clause 22.2.4.4 of IEEE-802.3. A 16-bit
shift register receives serial data applied to the
MDIO pin at the rising edge of the MDC clock signal.
Once the preamble is received, the station
management control logic looks for the start-of-
frame sequence and a read or write op-code,
followed by the PHYAD and REGAD fields. For a
read operation, the MDIO port becomes enabled as
an output and the register data is loaded into a shift
register for transmission. The 78Q2132 can work
with a one-bit preamble rather than the 32 bits
prescribed by IEEE-802.3. This allows for faster
programming of the registers. If a register does not
exist at an address indicated by the REGAD field or
if the PHYAD field does not match the 78Q2132
PHYAD indicated by the PHYAD pins, a read of the
MDIO port will return all ones. For a write operation,
the data is shifted in and loaded into the appropriate
register after the sixteenth data bit has been
received. Writes to registers not supported by the
78Q2132 are ignored.
Interrupt Pin
The 78Q2132 has an Interrupt pin (INTR) that is
asserted whenever any of the Twenty Four interrupt
bits of MR17.7:0 for 10BASE-T and P1R3 15:0 for
HomePNA are set. These interrupt bits can be
disabled via MR17.15:8 and MR19.12 Interrupt
Enable bits.
The Interrupt Level bit, MR16.14,
controls the active level of the INTR pin. When the
INTR pin is not asserted, the pin is held in a high
impedance state.
When the PHYAD field is all zeros, the Station
Management Entity (STA) is requesting a broadcast
data transaction.
All PHYs sharing the same
Management Interface must respond to this
broadcast request. The 78Q2132 responds to the
broadcast data transaction.
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