78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
10BASE-T Receive
specifically, 3,4,5 and 6 bits. Pulse positions are
assigned to the encoded bit groups in a manner that
causes more data bits to be encoded in positions
that are farther apart. This keeps both the average
and minimum bit rates higher.
The 78Q2132 receives Manchester encoded
10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a
smart squelch function. The slicer automatically
adjusts its level after valid data with the appropriate
levels are detected. Data is passed on to the
10BASE-T PLL where the clock is recovered, data is
re-timed and passed through a Manchester decoder.
From here data enters the serial to parallel converter
for transmission to the MAC via the media
independent interface. Interface to the twisted pair
media is through an external 100 ohm resistor and a
1:1 center-tapped transformer; no external filtering is
HomePNA 1.1 Compatibility
MR19.11 will reflect the version of HomePNA to be
utilized to set the Link Status bit MR1.2. When
MR19.11 is a logic zero, the device will behave as a
HomePNA v1.0 compliant PHY. This will result in
the Link Status bit MR1.2 always being logic one. If
MR19.11 is set to logic one, the device will behave
as a HomePNA 1.1 compliant PHY.
To enable link integrity checking as specified by
HomePNA v1.1, the PHY continually checks for
packet reception. Upon a lapse of packets greater
than 4seconds, the link status bit, MR1.2, is cleared.
required.
corrected in the internal circuitry.
Polarity information is detected and
Receive Signal
Also, for HomePNA v1.1 compatibility, the PHY can
be commanded to place a RUNT or MINIMUM
packet out at any time. These packets, along with
normal packets, indicate to other transceivers that
the link is up when sent at least every 2seconds.
The integrated signal qualifier has separate squelch and
un-squelch thresholds, and includes a built-in timer to
ensure fast and accurate signal detection and receive
noise rejection. Upon detection of two or more valid
10BASE-T pulses on the line receive port, the pass
indication, indicating the presence of valid receive signals
or data, will be asserted. When pass is asserted, the
signal detect threshold is lowered by about 60%, and all
adaptive circuits are released from their quiescent
operating conditions, allowing them to lock onto the
incoming data. In 10BASE-T operation, pass will be de-
asserted whenever no Manchester data is received. In
either case, the signal detect threshold will return to the
squelched level whenever the pass indication is de-
asserted. The pass signal is used internally to control the
operation of the receive clock recovery.
10BASE-T OPERATION
10BASE-T Transmit
The 78Q2132 takes 4 bit parallel NRZ data via the
MII interface and passes it through a parallel to
serial converter. The data is then passed through a
Manchester encoder and then on to the twisted pair
pulse shaping circuitry and the twisted pair drive
circuitry. An advanced pulse shaper employs a Gm-
C filter to pre-distort the output waveform to meet the
output voltage template and spectral content
requirements detailed in Clause 14 of IEEE-802.3.
Interface to the twisted pair media is through a
center-tapped 1.414:1 transformer with 100 ohm
load resistors; no external filtering is required.
During 10BASE-T idle periods, normal link pulses
(NLP) are transmitted. During auto-negotiation of
half or full duplex, fast link pulses (FLP) are
transmitted. When neither data nor link pulses are
being transmitted, the bias current to the transmitter
is cut to 1% of normal. This reduces the power
consumption during idle periods.
Receive Clock Recovery
In 10BASE-T mode, the 10MHz clock is recovered
using a PLL. For fast acquisition, the receive PLL is
locked onto the transmit reference clock during idle
receive periods. When Manchester-coded preambles
are detected, the PLL adjusts its phase and re-
synchronizes with the incoming Manchester data.
Polarity Correction
The 78Q2132 is capable of either automatic or
manual polarity reversal for 10BASE-T and auto-
negotiation.
Register bits MR16.5 and MR16.4
The 78Q2132 employs an onboard timer to prevent
control these features. The default is automatic
mode where MR16.5 is low and MR16.4 indicates if
the detection circuitry has inverted the input signal.
To enter manual mode, MR16.5 is set high and
MR16.4 will then control the signal polarity.
the MAC from capturing
a
network through
excessively long transmissions. When this timer is
exceeded the chip enters the Jabber State, and
transmission is disabled. The jabber state is exited
after the MII goes idle for 500ms ± 250ms.
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