78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
SQE Test
Upon receiving three more identical LCWs, with the
acknowledge bit set, the 78Q2132 configures itself
to either full duplex or half duplex, which ever is
common to the two link partners with Full Duplex
taking priority.
The 78Q2132 supports the signal quality error (SQE)
function detailed in IEEE-802.3. At an interval of 1m
s after each negative transition of the TXEN pin in
10BASE-T mode, the COL pin will go high for a
period of 1ms. This function can be disabled through
register bit MR16.11.
Once auto-negotiation is complete, register bit
MR18.10 will reflect the duplex mode that was
chosen.
If HomePNA mode is selected, auto-
Natural Loopback
negotiation is disabled and this bit has no meaning.
If auto-negotiation fails to establish a link for any
reason, register bit MR18.12 will reflect this and
auto-negotiation will restart from the beginning.
Writing a one to bit MR0.9, RANEG, will also cause
auto-negotiation to restart.
When the 78Q2132 is transmitting and not receiving
on the twisted pair media, data on the TXD pins is
looped back onto the RXD pins. During a collision,
signal from the analog receive pins is decoded and
sent to the digital RXD pins, as normal. The natural
loopback function can be enabled through register
bit MR16.10.
MEDIA INDEPENDENT INTERFACE
MII Transmit and Receive Operation
Auto-Negotiation
The 78Q2132 supports the auto-negotiation function
of Clause 28 of IEEE-802.3 for 10BASE-T half and
The MII interface on the 78Q2132 provides
independent transmit and receive paths for the
1Mb/s HomePNA interface and the 10Mb/s 10BASE-
T data rate as described in Clause 22 of the IEEE-
802.3 standard.
full duplex technologies.
This function can be
enabled via a pin strap to the device or through
registers. If the ANEGA pin is tied high, the auto-
negotiation function defaults to on and bit MR0.12,
ANEGEN, is high after reset. Software can disable
the auto-negotiation function by writing to bit
MR0.12. If the ANEGA pin is tied low the function
defaults to off and bit MR0.12 is set low after reset
and cannot be written.
The transmit clock, TX_CLK, provides the timing
reference for the transfer of TX_EN, and TXD[3:0],
signals from the MAC to the 78Q2132. TXD[3:0] is
captured on the rising edge of TX_CLK when
TX_EN is asserted.
The receive clock, RX_CLK, provides the timing
reference to transfer RX_DV, and RXD[3:0], signals
from the 78Q2132 to the MAC. RX_DV transitions
synchronously with respect to RX_CLK and is
asserted when the 78Q2132 is presenting valid data
on RXD[3:0].
The contents of MII Register MR4 are sent to the link
partner during auto-negotiation encoded in FLPs.
Technology ability bits MR4.9: 7 are not supported
and are permanently tied low. Bits MR4.6:5 reflect
the state of the TECH[2:0] pins.
After reset, software can disable the bits but they
cannot be enabled unless it’s corresponding
technology is permitted by the TECH pins.
General Purpose Serial Interface
The seven signals which comprise the GPSI are
TX_CLK, TX_EN, TX_DATA, RX_CLK, RX_DATA,
CRS, and CLSN. Of these, only TX_EN and
TX_DATA are inputs to the 2132; the other five are
outputs from the 2132.
With auto-negotiation enabled the 78Q2132 will start
sending FLPs at power-up, loss of link or a
command to restart, if the HomePNA mode is not
selected. At the same time it will look for either
10BASE-T idle or FLPs from its link partner. If
10BASE-T idle pattern is detected, the 78Q2132
realizes that its link partner is not capable of auto-
negotiation, falls into parallel detect mode and
configures itself to half-duplex mode. If FLPs are
detected, it decodes and analyzes the link code
word (LCW) transmitted by the link partner. When
three identical LCWs are received (ignoring the
acknowledge bit) the LCW is stored in register 5.
The transmit clock, TX_CLK, provides the timing
reference for the transfer of TX_EN and TX_DATA
signals from the MAC to the 2132. TX_DATA is
captured on the rising edge of TX_CLK when
TX_EN is asserted.
The receive clock, RX_CLK, provides the timing
reference to transfer the RX_DATA signal from the
2132
to
the
MAC.
RX_DATA
transitions
synchronously on the rising edge of RX_CLK.
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