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74VHCT373ASJX PDF预览

74VHCT373ASJX

更新时间: 2024-11-05 23:24:39
品牌 Logo 应用领域
其他 - ETC 锁存器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
7页 94K
描述
8-Bit D-Type Latch

74VHCT373ASJX 数据手册

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July 1997  
Revised April 1999  
74VHCT373A  
Octal D-Type Latch with 3-STATE Outputs  
5V systems and two supply systems such as battery back  
up. This circuit prevents device destruction due to mis-  
matched supply and input voltages.  
General Description  
The VHCT373A is an advanced high speed CMOS octal D-  
type latch with 3-STATE output fabricated with silicon gate  
CMOS technology. It achieves the high speed operation  
similar to equivalent Bipolar Schottky TTL while maintain-  
ing the CMOS low power dissipation. This 8-bit D-type  
latch is controlled by a latch enable input (LE) and an out-  
put enable input (OE). The latches appear transparent to  
data when latch enable (LE) is HIGH. When LE is LOW, the  
data that meets the setup time is latched. When the OE  
input is HIGH, the eight outputs are in a high impedance  
state.  
Note 1: Outputs in OFF-State.  
Features  
High speed: tPD = 7.7 ns (typ) at TA = 25°C  
High Noise Immunity: VIH = 2.0V, VIL = 0.8V  
Power Down Protection is provided on all inputs and  
outputs  
Low Power Dissipation:  
Protection circuits ensure that 0V to 7V can be applied to  
the input and output (Note 1) pins without regard to the  
supply voltage. This device can be used to interface 3V to  
I
CC = 4 µA (max) @ TA = 25°C  
Pin and Function Compatible with 74HCT373  
Ordering Code:  
Order Number  
74VHCT373AM  
74VHCT373ASJ  
74VHCT373AMTC  
74VHCT373AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
M20D  
MTC20  
N20A  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
D0–D7  
LE  
Description  
Data Inputs  
Latch Enable Input  
Output Enable Input  
3-STATE Outputs  
OE  
O0–O7  
© 1999 Fairchild Semiconductor Corporation  
DS500027.prf  
www.fairchildsemi.com  

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