Datasheet > 74VHCT125A_04

74VHCT125A_04

更新时间： 2024-01-26 07:10:11

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
12页	229K
描述
QUAD BUS BUFFERS (3-STATE)

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74VHCT125A_04 数据手册

74VHCT125A

QUAD BUS BUFFERS (3-STATE)

■

HIGH SPEED: t = 3.8 ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

■

COMPATIBLE WITH TTL OUTPUTS:

= 2V (MIN.), V = 0.8V (MAX)

POWER DOWN PROTECTION ON INPUTS

& OUTPUTS

SOP

TSSOP

T & R

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8 mA (MIN)

Table 1: Order Codes

PACKAGE

BALANCED PROPAGATION DELAYS:

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 4.5V to 5.5V

SOP

74VHCT125AMTR

74VHCT125ATTR

TSSOP

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 125

■

IMPROVED LATCH-UP IMMUNITY

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V since all

inputs are equipped with TTL threshold.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

LOW NOISE: V

= 0.8V (MAX.)

OLP

DESCRIPTION

The 74VHCT125A is an advanced high-speed

CMOS QUAD BUS BUFFERS fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology.

The device requires the 3-STATE control input G

to be set high to place the output in to the high

impedance state.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 6

1/12

December 2004

12 3 4 5 6 7...12

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