Datasheet > 74VHCT08A_04

74VHCT08A_04

更新时间： 2024-11-05 05:05:51

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
11页	221K
描述
QUAD 2-INPUT AND GATE

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74VHCT08A_04 数据手册

74VHCT08A

QUAD 2-INPUT AND GATE

■

HIGH SPEED: t = 4.7 ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

■

COMPATIBLE WITH TTL OUTPUTS:

= 2V (MIN.), V = 0.8V (MAX)

POWER DOWN PROTECTION ON INPUTS

& OUTPUTS

SOP

TSSOP

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8 mA (MIN)

Table 1: Order Codes

PACKAGE

BALANCED PROPAGATION DELAYS:

PLH

PHL

T & R

OPERATING VOLTAGE RANGE:

(OPR) = 4.5V to 5.5V

SOP

74VHCT08AMTR

74VHCT08ATTR

TSSOP

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 08

■

IMPROVED LATCH-UP IMMUNITY

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V since all

inputs are equipped with TTL threshold.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

LOW NOISE: V

= 0.8V (MAX.)

OLP

DESCRIPTION

The 74VHCT08A is an advanced high-speed

CMOS QUAD 2-INPUT AND GATE fabricated

with sub-micron silicon gate and double-layer

metal wiring C MOS technology.

The internal circuit is composed of 2 stages

including buffer output, which provides high noise

immunity and stable output.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 4

1/11

December 2004

12 3 4 5 6 7...11

中文翻译

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