November 1992
Revised February 2005
74VHC86
Quad 2-Input Exclusive-OR Gate
General Description
Features
The VHC86 is an advanced high speed CMOS Quad
Exclusive OR Gate fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
■ High Speed: tPD 4.8 ns (typ) at VCC 5V
■ Low Power Dissipation: ICC A (Max.) @ TA 25 C
2
■ High Noise Immunity: VNIH VNIL 28% VCC (Min.)
■ Power down protection is provided on all inputs
■ Low Noise: VOLP 0.8V (Max.)
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and on two supply systems such as battery back up. This
circuit prevents device destruction due to mismatched sup-
ply and input voltages.
■ Pin and Function Compatible with 74HC86
Ordering Code:
Package
Order Number
Package Description
Number
74VHC86M
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC86SJ
74VHC86MTC
MTC14
MTC14
74VHC86MTCX_NL
(Note 1)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC86N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STS-020B). Device available in Tape and Reel only.
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Table
Pin Descriptions
A
L
B
L
O
L
Pin Names
A0–A3
Description
Inputs
L
H
L
H
H
L
H
H
B0–B3
Inputs
H
O0–O3
Outputs
© 2005 Fairchild Semiconductor Corporation
DS011517
www.fairchildsemi.com