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74VHC86T PDF预览

74VHC86T

更新时间: 2024-11-20 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 58K
描述
QUAD EXCLUSIVE OR GATE

74VHC86T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.13系列:AHC/VHC
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:XOR GATE最大I(ol):0.008 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

74VHC86T 数据手册

 浏览型号74VHC86T的Datasheet PDF文件第2页浏览型号74VHC86T的Datasheet PDF文件第3页浏览型号74VHC86T的Datasheet PDF文件第4页浏览型号74VHC86T的Datasheet PDF文件第5页浏览型号74VHC86T的Datasheet PDF文件第6页浏览型号74VHC86T的Datasheet PDF文件第7页 
74VHC86  
QUAD EXCLUSIVE OR GATE  
PRELIMINARY DATA  
HIGH SPEED:tPD =4.8ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
I
CC =2 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
NIH = VNIL =28% VCC (MIN.)  
V
M
T
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES86  
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHC86M  
74VHC86T  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
DESCRIPTION  
The 74VHC86 is an advanced high-speed CMOS  
QUAD EXCLUSIVE OR GATE fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
June 1999  

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