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74VHC138MTR PDF预览

74VHC138MTR

更新时间: 2024-11-02 04:48:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 323K
描述
3 TO 8 LINE DECODER (INVERTING)

74VHC138MTR 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.08
系列:AHC/VHC输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.008 A
湿度敏感等级:3功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:11.5 ns传播延迟(tpd):18 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74VHC138MTR 数据手册

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74VHC138  
3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED: t = 5.7ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
T & R  
V
CC  
SOP  
74VHC138MTR  
74VHC138TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 138  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
Tree enable inputs are provided to ease cascade  
connection and application of address decoders  
for memory systems.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHC138 is an advanced high-speed  
CMOS 3 TO 8 LINE DECODER (INVERTING)  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS technology.  
If the device is enabled, 3 binary select (A, B, and  
C) determine which one of the outputs will go low.  
If enable input G1 is held low or either G2A or G2B  
is held high, the decoding function is inhibited and  
all the 8 outputs go to high.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/12  
November 2004  

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