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74VHC139 PDF预览

74VHC139

更新时间: 2024-09-28 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器解复用器
页数 文件大小 规格书
6页 76K
描述
Dual 2-to-4 Decoder/Demultiplexer

74VHC139 数据手册

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November 1992  
Revised April 1999  
74VHC139  
Dual 2-to-4 Decoder/Demultiplexer  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery back up. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC139 is an advanced high speed CMOS Dual 2-to-  
4
Decoder/Demultiplexer fabricated with silicon gate  
CMOS technology. It achieves the high speed operation  
similar to equivalent Bipolar Schottky TTL while maintain-  
ing the CMOS low power dissipation.  
Features  
High Speed: tPD = 5.0 ns (typ) at TA = 25°C  
Low power dissipation: ICC = 4 µA (Max.) at TA = 25°C  
High noise immunity: VNIH = VNIL = 28% VCC (Min.)  
The active LOW enable input can be used for gating or it  
can be used as a data input for demultiplexing applications.  
When the enable input is held HIGH, all four outputs are  
fixed at a HIGH logic level independent of the other inputs.  
An input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
Power down protection is provided on all inputs  
Pin and function compatible with 74HC139  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC139M  
74VHC139SJ  
74VHC139MTC  
74VHC139N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Description  
Pin Names  
A0, A1  
E
Description  
Address Inputs  
Enable Inputs  
Outputs  
O0–O3  
Truth Table  
Inputs  
Outputs  
E
A0  
A1  
O0  
O1  
O2  
O3  
H
L
L
L
L
X
L
X
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
© 1999 Fairchild Semiconductor Corporation  
DS011521.prf  
www.fairchildsemi.com  

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