74VHC139T

更新时间： 2024-09-29 22:56:23

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器解复用器
页数	文件大小	规格书
8页	65K
描述
DUAL 2 TO 4 DECODER/DEMULTIPLEXER

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中文翻译

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数据手册

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74VHC139T 数据手册

74VHC139

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

■

HIGH SPEED:t_PD=5.0ns (TYP.) at V_CC= 5V

LOW POWER DISSIPATION:

I_CC=4 µA (MAX.) at T_A=25 ^oC

HIGH NOISEIMMUNITY:

■

V_NIH= V_NIL=28% V_CC(MIN.)

POWERDOWN PROTECTIONON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 8 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

■

(Micro Package)

(TSSOPPackage)

ORDER CODES :

74VHC139M

74VHC139T

■

OPERATING VOLTAGERANGE:

gating or as a data input for demultiplexing

applications. While the enable input is held high,

all four outputs are high independently of the

other inputs.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

V_CC(OPR)= 2V to 5.5V

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES139

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHC139 is an advanced high-speed

CMOS DUAL 2 TO

LINE DECODER/

DEMULTIPLEXER fabricated with sub-micron

silicon gate and double-layermetal wiring C²MOS

technology.

The active low enable input can be used for

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8

June 1999

12 3 4 5 6 7 8

中文翻译

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与74VHC139T相关器件

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