Datasheet > 74VCX32500GX

74VCX32500GX

更新时间： 2024-11-24 23:24:35

品牌	Logo	应用领域
其他 - ETC		总线收发器
页数	文件大小	规格书
8页	83K
描述
18-Bit Bus Transceiver

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数据手册

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74VCX32500GX 数据手册

March 2001

Revised September 2001

74VCX32500

Low Voltage 36-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

General Description

The VCX32500 is an 36-bit universal bus transceiver which

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched, and clocked modes.

Features

■ 1.65V–3.6V V_CCsupply operation

■ 3.6V tolerant inputs and outputs

■ t_PD(A to B, B to A)

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

device operates in the transparent mode when LEAB is

HIGH. When LEAB is LOW, the A data is latched if CLKAB

is held at a HIGH or LOW logic level. If LEAB is LOW, the A

bus data is stored in the latch/flip-flop on the HIGH-to-LOW

transition of CLKAB. When OEAB is HIGH, the outputs are

active. When OEAB is LOW, the outputs are in a high-

impedance state.

2.9 ns max for 3.0V to 3.6V V_CC

3.5 ns max for 2.3V to 2.7V V_CC

7.0 ns max for 1.65V to 1.95V V_CC

■ Power-down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ Static Drive (I_OH/I_OL

)

±24 mA @ 3.0V V_CC

±18 mA @ 2.3V V_CC

±6 mA @ 1.65V V_CC

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

plementary (OEAB is active HIGH and OEBA is active

LOW).

■ Uses patented noise/EMI reduction circuitry

■ Latchup performance exceeds 300 mA

■ ESD performance:

The VCX32500 is designed for low voltage (1.65V to 3.6V)

V_CCapplications with I/O capability up to 3.6V.

Human body model > 2000V

The 74VCX32500 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Machine model >200V

■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Note 1: To ensure the high-impedance state during power up or power

down, OEBA should be tied to V_CCthrough a pull-up resistor and OEAB

should be tied to GND through a pull-down resistors; the minimum value of

the resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Order Number Package Number

Package Description

74VCX32500GX

(Note 2)

BGA114A

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[Tape and Reel]

Note 2: BGA package available in Tape and Reel only.

DS500403

www.fairchildsemi.com

12 3 4 5 6 7 8

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74VCX32MX	FAIRCHILD	获取价格	Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs
74VCX38	FAIRCHILD	获取价格	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Ou
74VCX38_05	FAIRCHILD	获取价格	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Ou
74VCX38BQX	FAIRCHILD	获取价格	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Ou
74VCX38M	FAIRCHILD	获取价格	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Ou
74VCX38MTC	FAIRCHILD	获取价格	Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Ou

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