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74SSTUB32864AZKER PDF预览

74SSTUB32864AZKER

更新时间： 2024-11-10 02:58:43
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器
页数 文件大小 规格书
19页 519K
描述
25-BIT CONFIGURABLE REGISTERED BUFFER

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74SSTUB32864AZKER 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：GREEN, PLASTIC, LFBGA-96针数：96
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：7.79系列：SSTU
JESD-30 代码：R-PBGA-B96JESD-609代码：e1
长度：13.5 mm逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：4100000000 Hz最大I（ol）：0.008 A
湿度敏感等级：3位数：25
功能数量：1端子数量：96
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA96,6X16,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.8 VProp。Delay @ Nom-Sup：0.7 ns
传播延迟（tpd）：0.7 ns认证状态：Not Qualified
座面最大高度：1.4 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：5.5 mm
最小 fmax：410 MHzBase Number Matches：1

74SSTUB32864AZKER 数据手册

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74SSTUB32864A  
www.ti.com  
SCAS838–OCTOBER 2006  
25-BIT CONFIGURABLE REGISTERED BUFFER  
FEATURES  
•
Output Edge-Control Circuitry Minimizes  
Switching Noise in an Unterminated Line  
•
Member of the Texas Instruments  
Widebus+™ Family  
•
•
•
Supports SSTL_18 Data Inputs  
•
•
Pinout Optimizes DDR2 DIMM PCB Layout  
Differential Clock (CLK and CLK) Inputs  
Configurable as 25-Bit 1:1 or 14-Bit 1:2  
Registered Buffer  
Supports LVCMOS Switching Levels on the  
Control and RESET Inputs  
•
Chip-Select Inputs Gate the Data Outputs  
from Changing State and Minimizes System  
Power Consumption  
•
RESET Input Disables Differential Input  
Receivers, Resets All Registers, and Forces  
All Outputs Low  
DESCRIPTION  
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the  
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout  
configuration, two devices per DIMM are required to drive 18 SDRAM loads.  
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are  
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the  
open-drain error (QERR) output.  
The 74SSTUB32864A operates from a differential clock (CLK and CLK). Data are registered at the crossing of  
CLK going high and CLK going low.  
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to  
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to  
14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired  
to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration,  
the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.  
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and  
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is  
cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input  
receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required  
to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the  
time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the  
74SSTUB32864A ensures that the outputs remain low, thus ensuring there will be no glitches on the output.  
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the  
low state during power up.  
The device supports low-power standby operation. When RESET is low, the differential input receivers are  
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when  
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always  
must be held at a valid logic high or low level.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
0°C to 70°C  
LFBGA–ZKE Tape and reel  
74SSTUB32864AZKER  
SB864A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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74SSTUB32864AZKER 替代型号

型号 品牌 替代类型 描述 数据表
SN74SSTUB32864ZKER TI

完全替代

 25-BIT CONFIGURABLE REGISTERED BUFFER
SN74SSTUB32866ZWLR TI

完全替代

 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
SN74SSTUB32866ZKER TI

完全替代

 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

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