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74SSTV16859NL8 PDF预览

74SSTV16859NL8

更新时间: 2024-11-09 14:47:07
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
6页 60K
描述
Bus Driver, PQCC56

74SSTV16859NL8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:QCCN, LCC56,.31SQ,20Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
JESD-30 代码:S-PQCC-N56JESD-609代码:e0
逻辑集成电路类型:BUS DRIVER湿度敏感等级:3
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC56,.31SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER
电源:2.5 V认证状态:Not Qualified
子类别:Other Logic ICs标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

74SSTV16859NL8 数据手册

 浏览型号74SSTV16859NL8的Datasheet PDF文件第2页浏览型号74SSTV16859NL8的Datasheet PDF文件第3页浏览型号74SSTV16859NL8的Datasheet PDF文件第4页浏览型号74SSTV16859NL8的Datasheet PDF文件第5页浏览型号74SSTV16859NL8的Datasheet PDF文件第6页 
13-BIT TO 26-BIT REGISTERED  
BUFFER WITH SSTL I/O  
IDT74SSTV16859  
FEATURES:  
DESCRIPTION:  
• 2.3V to 2.7V Operation  
TheSSTV16859isa13-bitto26-bitregisteredbufferdesignedfor2.3V-  
2.7VVDD andsupportslowstandbyoperation. Alldatainputsandoutputs  
are SSTL_2 level compatible with JEDEC standard for SSTL_2.  
RESETisanLVCMOSinputsinceitmustoperatepredictablyduringthe  
power-upphase.RESET,whichcanbeoperatedindependentofCLKand  
CLK, must be held in the low state during power-up in order to ensure  
predictable outputs (low state) before a stable clock has been applied.  
RESET, when in the low state, will disable all input receivers, reset all  
registers,andforcealloutputstoalowstate,beforeastableclockhasbeen  
applied. Withinputsheldlowandastableclockapplied,outputswillremain  
low during the Low-to-High transition of RESET.  
• SSTL_2 Class II style data inputs/outputs  
• Differential CLK input  
RESET control compatible with LVCMOS levels  
• Latch-up performance exceeds 100mA  
• ESD >2000V per MIL-STD-883, Method 3015; >200V using  
machine model (C = 200pF, R = 0)  
• Available in 56 pin VFQFPN and 64 pin TSSOP packages  
APPLICATIONS:  
• Ideally suited for DIMM DDR registered applications  
FUNCTIONALBLOCKDIAGRAM  
51  
RESET  
48  
CLK  
49  
CLK  
45  
VREF  
35  
D1  
16  
Q1A  
1D  
C1  
32  
R
Q1B  
TO 12 OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 2002  
1
c
2003 Integrated Device Technology, Inc.  
DSC-5947/6  

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