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74LVT240PW PDF预览

74LVT240PW

更新时间: 2024-11-07 11:13:11
品牌 Logo 应用领域
安世 - NEXPERIA 驱动输入元件信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
12页 226K
描述
3.3 V Octal inverting buffer/line driver; 3-stateProduction

74LVT240PW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.07Is Samacsys:N
其他特性:INPUTS CAN BE DRIVEN BY 3.3V OR 5V COMPONENTS系列:LVT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260最大电源电流(ICC):12 mA
传播延迟(tpd):5 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74LVT240PW 数据手册

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74LVT240  
3.3 V Octal inverting buffer/line driver; 3-state  
Rev. 4 — 28 July 2021  
Product data sheet  
1. General description  
The 74LVT240 is an 8-bit inverting buffer/line driver with 3-state outputs. The device can be used  
as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE),  
each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to  
define unused inputs.  
2. Features and benefits  
Octal bus interface  
3-state buffers  
Wide supply voltage range from 2.7 to 3.6 V  
Overvoltage tolerant inputs to 5.5 V  
BiCMOS high speed and output drive  
Output capability: +64 mA and -32 mA  
Direct interface with TTL levels  
Input and output interface capability to systems at 5 V supply  
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs  
Live insertion and extraction permitted  
Power-up 3-state  
No bus current loading when output is tied to 5 V bus  
IOFF circuitry provides partial Power-down mode operation  
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B  
Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)  
ESD protection:  
MIL STD 883 method 3015: exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to 85 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
-40 °C to +85 °C  
Name  
Description  
Version  
74LVT240D  
SO20  
plastic small outline package; 20 leads;  
body width 7.5 mm  
SOT163-1  
74LVT240PW  
-40 °C to +85 °C  
TSSOP20  
plastic thin shrink small outline package; 20 leads;  
body width 4.4 mm  
SOT360-1  
 
 
 

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