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74LVT16374ADGG,112 PDF预览

74LVT16374ADGG,112

更新时间: 2024-11-07 09:54:55
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
19页 218K
描述
74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48-Pin

74LVT16374ADGG,112 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.36
系列:LVTJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:12.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.064 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:5 ns
传播延迟(tpd):5.6 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74LVT16374ADGG,112 数据手册

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74LVT16374A; 74LVTH16374A  
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state  
Rev. 10 — 2 April 2012  
Product data sheet  
1. General description  
The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for  
CC operation at 3.3 V.  
V
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state  
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the  
positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic  
levels set up at the nDn inputs.  
2. Features and benefits  
16-bit edge-triggered flip-flop  
3-state buffers  
Output capability: +64 mA and 32 mA  
TTL input and output switching levels  
Input and output interface capability to systems at 5 V supply  
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused  
inputs  
Live insertion and extraction permitted  
Power-up reset  
Power-up 3-state  
No bus current loading when output is tied to 5 V bus  
Latch-up protection:  
JESD78B Class II exceeds 500 mA  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  

74LVT16374ADGG,112 替代型号

型号 品牌 替代类型 描述 数据表
74LVTH16374ADGG,18 NXP

完全替代

74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48
74LVT16374ADGG,118 NXP

完全替代

74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48

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