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74LVT16374ADL,112 PDF预览

74LVT16374ADL,112

更新时间: 2024-09-15 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
19页 221K
描述
74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state SSOP 48-Pin

74LVT16374ADL,112 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.15
Is Samacsys:N其他特性:OUTSIDE NORTH AMERICA, PART NUMBER
系列:LVTJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:15.875 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.064 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TUBE峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):6 mA
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5.6 ns
认证状态:Not Qualified座面最大高度:2.8 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

74LVT16374ADL,112 数据手册

 浏览型号74LVT16374ADL,112的Datasheet PDF文件第2页浏览型号74LVT16374ADL,112的Datasheet PDF文件第3页浏览型号74LVT16374ADL,112的Datasheet PDF文件第4页浏览型号74LVT16374ADL,112的Datasheet PDF文件第5页浏览型号74LVT16374ADL,112的Datasheet PDF文件第6页浏览型号74LVT16374ADL,112的Datasheet PDF文件第7页 
74LVT16374A; 74LVTH16374A  
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state  
Rev. 10 — 2 April 2012  
Product data sheet  
1. General description  
The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for  
CC operation at 3.3 V.  
V
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state  
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the  
positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic  
levels set up at the nDn inputs.  
2. Features and benefits  
16-bit edge-triggered flip-flop  
3-state buffers  
Output capability: +64 mA and 32 mA  
TTL input and output switching levels  
Input and output interface capability to systems at 5 V supply  
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused  
inputs  
Live insertion and extraction permitted  
Power-up reset  
Power-up 3-state  
No bus current loading when output is tied to 5 V bus  
Latch-up protection:  
JESD78B Class II exceeds 500 mA  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
 
 

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