74LVT16244MTD_NL

更新时间： 2024-10-26 13:04:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		驱动器
页数	文件大小	规格书
7页	92K
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中文翻译

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数据手册

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74LVT16244MTD_NL 数据手册

March 1999

Revised June 2005

74LVT16244 • 74LVTH16244

Low Voltage16-Bit Buffer/Line Driver

with 3-STATE Outputs

General Description

Features

■ Input and output interface capability to systems at

The LVT16244 and LVTH16244 contain sixteen non-invert-

ing buffers with 3-STATE outputs designed to be employed

as a memory and address driver, clock driver, or bus ori-

ented transmitter/receiver. The device is nibble controlled.

Individual 3-STATE control inputs can be shorted together

for 8-bit or 16-bit operation.

5V V_CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16244),

also available without bushold feature (74LVT16244).

■ Live insertion/extraction permitted

The LVTH16244 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Outputs source/sink 32 mA/ 64 mA

■ Functionally compatible with the 74 series 16244

■ Latch-up performance exceeds 500 mA

■ ESD performance:

These buffers and line drivers are designed for low-voltage

(3.3V) V_CCapplications, but with the capability to provide a

TTL interface to a 5V environment. The LVT16244 and

LVTH16244 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining a low power dissipation

Human-body model 2000V

Machine model 200V

Charged-drive model 1000V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Package

Order Number

Package Description

Number

74LVT16244G

(Note 1)(Note 2)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVT16244MEA

(Note 2)

MS48A

MTD48

BGA54A

MS48A

MTD48

74LVT16244MTD

(Note 2)

74LVTH16244G

(Note 1)(Note 2)

74LVTH16244MEA

(Note 2)

74LVTH16244MTD

(Note 2)

Note 1: Ordering code “G” indicates Trays.

Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

DS500151

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

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与74LVT16244MTD_NL相关器件

型号	品牌	获取价格	描述	数据表
74LVT16244MTDX	FAIRCHILD	获取价格	Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
74LVT16245	FAIRCHILD	获取价格	Low Voltage 16-Bit Transceiver with 3-STATE Outputs
74LVT16245AMEA	ETC	获取价格	Dual 8-bit Bus Transceiver
74LVT16245AMEAX	ETC	获取价格	Dual 8-bit Bus Transceiver
74LVT16245AMTD	ETC	获取价格	Dual 8-bit Bus Transceiver
74LVT16245AMTDX	ETC	获取价格	Dual 8-bit Bus Transceiver
74LVT16245B	NXP	获取价格	3.3V ABT 16-bit transceiver 3-State
74LVT16245BBQ	NXP	获取价格	3.3 V 16-bit transceiver; 3-state
74LVT16245BBQ,515	NXP	获取价格	74LVT16245BBQ
74LVT16245BBX	NXP	获取价格	IC LVT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PBCC60, 4 X 6 MM, 0.50 MM HEIGHT, 0.50

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