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74LVT16244MTDX PDF预览

74LVT16244MTDX

更新时间： 2024-11-20 12:52:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 92K
描述
Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs

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中文翻译

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74LVT16244MTDX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP48,.3,20
针数：48Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.33
控制类型：ENABLE LOW系列：LVT
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
长度：12.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：2位数：4
功能数量：4端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：5 mA
Prop。Delay @ Nom-Sup：3.5 ns传播延迟（tpd）：3.9 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

74LVT16244MTDX 数据手册

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March 1999  
Revised June 2005  
74LVT16244 • 74LVTH16244  
Low Voltage16-Bit Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT16244 and LVTH16244 contain sixteen non-invert-  
ing buffers with 3-STATE outputs designed to be employed  
as a memory and address driver, clock driver, or bus ori-  
ented transmitter/receiver. The device is nibble controlled.  
Individual 3-STATE control inputs can be shorted together  
for 8-bit or 16-bit operation.  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16244),  
also available without bushold feature (74LVT16244).  
■ Live insertion/extraction permitted  
The LVTH16244 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
■ Outputs source/sink 32 mA/ 64 mA  
■ Functionally compatible with the 74 series 16244  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
These buffers and line drivers are designed for low-voltage  
(3.3V) VCC applications, but with the capability to provide a  
TTL interface to a 5V environment. The LVT16244 and  
LVTH16244 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining a low power dissipation  
Human-body model 2000V  
Machine model 200V  
Charged-drive model 1000V  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVT16244G  
(Note 1)(Note 2)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVT16244MEA  
(Note 2)  
MS48A  
MTD48  
BGA54A  
MS48A  
MTD48  
74LVT16244MTD  
(Note 2)  
74LVTH16244G  
(Note 1)(Note 2)  
74LVTH16244MEA  
(Note 2)  
74LVTH16244MTD  
(Note 2)  
Note 1: Ordering code “G” indicates Trays.  
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS500151  
www.fairchildsemi.com  
1234567

中文翻译

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74LVT16244MTDX 替代型号

型号 品牌 替代类型 描述 数据表
74LVT16244MTD FAIRCHILD

完全替代

 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
SN74LVTH162244DGGR TI

功能相似

 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LVTH16244ADGGR TI

功能相似

 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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