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74LVCH32374AEC/G,5 PDF预览

74LVCH32374AEC/G,5

更新时间: 2024-11-05 14:37:23
品牌 Logo 应用领域
恩智浦 - NXP 驱动逻辑集成电路触发器
页数 文件大小 规格书
15页 120K
描述
74LVCH32374A - 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin

74LVCH32374AEC/G,5 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:PLASTIC, FBGA-96针数:96
Reach Compliance Code:compliant风险等级:5.46
系列:LVC/LCX/ZJESD-30 代码:R-PBGA-B96
长度:13.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:120000000 Hz
最大I(ol):0.024 A湿度敏感等级:2
位数:8功能数量:4
端口数量:2端子数量:96
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA96,6X16,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:7 ns传播延迟(tpd):6.4 ns
认证状态:Not Qualified座面最大高度:1.5 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:5.5 mmBase Number Matches:1

74LVCH32374AEC/G,5 数据手册

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74LVCH32374A  
32-bit edge-triggered D-type flip-flop with 5 V tolerant  
inputs/outputs; 3-state  
Rev. 3 — 18 December 2012  
Product data sheet  
1. General description  
The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs  
for each flip-flop and 3-state outputs for bus oriented applications. The device consists of  
4 sections of 8 edge-triggered flip-flops. A clock (pin nCP) input and an output enable  
input (pin nOE) are provided per 8-bit section. The flip-flops will store the state of their  
individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH  
nCP transition. When pin nOE is LOW, the contents of the flip-flops are available at the  
outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state.  
Operation of pin nOE does not affect the state of the flip-flops. The inputs can be driven  
from either 3.3 V or 5 V devices. In 3-state operation, the outputs can handle 5 V. These  
features allow the use of these devices in a mixed 3.3 V or 5 V environment.  
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused  
inputs.  
2. Features and benefits  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Multibyte flow-through standard pin-out architecture  
Multiple low inductance supply pins for minimum noise and ground bounce  
Direct interface with TTL levels  
All data inputs have bus hold  
High impedance when VCC = 0 V  
Latch-up performance exceeds 500 mA per JESD 78 Class II  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
Packaged in plastic fine-pitch ball grid array package  
 
 

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