Datasheet > 74LVCH2T45DC

74LVCH2T45DC

更新时间： 2023-09-03 20:28:01

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
33页	413K
描述
Dual supply translating transceiver; 3-stateProduction

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74LVCH2T45DC 数据手册

74LVC2T45; 74LVCH2T45

Dual supply translating transceiver; 3-state

Rev. 12 — 1 March 2023

Product data sheet

1. General description

The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state

outputs that enable bidirectional level translation. They feature two 2-bits input-output ports

(nA and nB), a direction control input (DIR) and dual supply pins (V_CC(A)and V_CC(B)). Both V_CC(A)

and V_CC(B)can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable

for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V).

Pins nA and DIR are referenced to V_CC(A)and pins nB are referenced to V_CC(B). A HIGH on DIR

allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The devices are fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing any damaging backflow current through the device when it is

powered down. In suspend mode when either V_CC(A)or V_CC(B)are at GND level, both A port and

B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid logic

level.

2. Features and benefits

•

Wide supply voltage range:

•

V_CC(A): 1.2 V to 5.5 V

V_CC(B): 1.2 V to 5.5 V

•

High noise immunity

Complies with JEDEC standards:

•

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM JESD22-A114F Class 3A exceeds 4000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

Maximum data rates:

•

420 Mbps (3.3 V to 5.0 V translation)

210 Mbps (translate to 3.3 V))

140 Mbps (translate to 2.5 V)

75 Mbps (translate to 1.8 V)

60 Mbps (translate to 1.5 V)

•

Suspend mode

Latch-up performance exceeds 100 mA per JESD 78 Class II

±24 mA output drive (V_CC= 3.0 V)

Inputs accept voltages up to 5.5 V

Low power consumption: 16 μA maximum I_CC

I_OFFcircuitry provides partial Power-down mode operation

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...33

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与74LVCH2T45DC相关器件

型号	品牌	获取价格	描述	数据表
74LVCH2T45DC-Q100	NEXPERIA	获取价格	Dual supply translating transceiver; 3-state
74LVCH2T45GD	NXP	获取价格	Dual supply translating transceiver; 3-state
74LVCH2T45GD,125	NXP	获取价格	74LVC2T45; 74LVCH2T45 - Dual supply translating transceiver; 3-state SON 8-Pin
74LVCH2T45GF	NXP	获取价格	Dual supply translating transceiver; 3-state
74LVCH2T45GF,115	NXP	获取价格	74LVC2T45; 74LVCH2T45 - Dual supply translating transceiver; 3-state SON 8-Pin
74LVCH2T45GM	NXP	获取价格	Dual supply translating transceiver; 3-state
74LVCH2T45GM,125	NXP	获取价格	74LVC2T45; 74LVCH2T45 - Dual supply translating transceiver; 3-state QFN 8-Pin
74LVCH2T45GN	NXP	获取价格	Dual supply translating transceiver; 3-state
74LVCH2T45GN	NEXPERIA	获取价格	Dual supply translating transceiver; 3-stateProduction
74LVCH2T45GS	NXP	获取价格	Dual supply translating transceiver; 3-state

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