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74LVC841ADB,118 PDF预览

74LVC841ADB,118

更新时间: 2024-11-07 14:22:11
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
21页 134K
描述
74LVC841A - 10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state SSOP2 24-Pin

74LVC841ADB,118 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SSOP2包装说明:SSOP, SSOP24,.3
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:8.2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:10
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):11 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
Base Number Matches:1

74LVC841ADB,118 数据手册

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74LVC841A  
10-bit transparent latch with 5 V tolerant inputs/outputs;  
3-state  
Rev. 03 — 24 May 2004  
Product data sheet  
1. General description  
The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and  
superior to most advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can  
handle 5 V. This feature allows the use of these devices as translators in a mixed  
3.3 V and 5 V environment.  
The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each  
latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and  
an output enable (pin OE) input are common to all internal latches. The 74LVC841A  
consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at  
the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch  
output will change each time its corresponding D-input changes. When pin LE is LOW the  
latches store the information that was present at the D-inputs a set-up time preceding the  
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the ten latches  
are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance  
OFF-state. Operation of the pin OE input does not affect the state of the latches.  
2. Features  
5 V tolerant inputs/outputs; for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
Inputs accept voltages up to 5.5 V  
CMOS low power consumption  
Direct interface with TTL levels  
Flow-through pin-out architecture  
Complies with JEDEC standard JESD8B/JESD36  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
 
 

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