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74LVC86A PDF预览

74LVC86A

更新时间: 2024-11-07 04:47:51
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
11页 238K
描述
LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE HIGH PERFORMANCE

74LVC86A 数据手册

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74LVC86A  
LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE  
HIGH PERFORMANCE  
5V TOLERANT INPUTS  
HIGH SPEED: t = 4.2ns (MAX.) at V = 3V  
PD  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN) at V = 3V  
OH  
OL  
CC  
SOP  
TSSOP  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 1.65V to 3.6V (1.2V Data  
T & R  
V
CC  
SOP  
74LVC86AMTR  
74LVC86ATTR  
Retention)  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 86  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
V
operations and low power and low noise  
CC  
applications.  
It can be interfaced to 5V signal environment for  
inputs in mixed 3.3/5V system.  
It has more speed performance at 3.3V than 5V  
AC/ACT family, combined with a lower power  
consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
DESCRIPTION  
The 74LVC86A is a low voltage CMOS QUAD  
EXCLUSIVE  
sub-micron silicon gate and double-layer metal  
wiring C MOS technology. It is ideal for 1.65 to 3.6  
OR  
GATE  
fabricated  
with  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/11  
July 2004  

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