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74LVC4245AD-Q100 PDF预览

74LVC4245AD-Q100

更新时间: 2024-10-01 01:10:47
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
17页 830K
描述
Octal dual supply translating transceiver; 3-state

74LVC4245AD-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
其他特性:IT ALSO OPERATES AT SUPPLY VOLTAGE A: 1.5 TO 5.5V系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G24长度:15.4 mm
逻辑集成电路类型:BUS TRANSCEIVER湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):8.5 ns
筛选级别:AEC-Q100座面最大高度:2.65 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

74LVC4245AD-Q100 数据手册

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74LVC4245A-Q100  
Octal dual supply translating transceiver; 3-state  
Rev. 1 — 20 October 2014  
Product data sheet  
1. General description  
The 74LVC4245A-Q100 is an octal dual supply translating transceiver featuring  
non-inverting 3-state bus compatible outputs in both send and receive directions. It is  
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply  
environment.  
The device features an output enable input (pin OE) for easy cascading and a  
send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the  
buses are effectively isolated.  
In suspend mode, when VCC(A) is zero, there is no current flow from one supply to the  
other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be  
smaller than Vdiode (typical 0.7 V).  
VCC(A) VCC(B), except in suspend mode.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
5 V tolerant inputs/outputs, for interfacing with 5 V logic  
Wide supply voltage range:  
3 V bus (VCC(B)): 1.5 V to 3.6 V  
5 V bus (VCC(A)): 1.5 V to 5.5 V  
CMOS low-power consumption  
Direct interface with TTL levels  
Inputs accept voltages up to 5.5 V  
High-impedance when VCC(A) = 0 V  
Complies with JEDEC standard no. JESD8B/JESD36  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  

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