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74LVC4245APW-T PDF预览

74LVC4245APW-T

更新时间: 2024-09-30 20:32:59
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件
页数 文件大小 规格书
17页 102K
描述
IC LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24, Bus Driver/Transceiver

74LVC4245APW-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.1其他特性:PORT B OPERATING AT 1.5 TO 3.6 VOLTS
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.8 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):8.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30翻译:3V & 5V
宽度:4.4 mmBase Number Matches:1

74LVC4245APW-T 数据手册

 浏览型号74LVC4245APW-T的Datasheet PDF文件第2页浏览型号74LVC4245APW-T的Datasheet PDF文件第3页浏览型号74LVC4245APW-T的Datasheet PDF文件第4页浏览型号74LVC4245APW-T的Datasheet PDF文件第5页浏览型号74LVC4245APW-T的Datasheet PDF文件第6页浏览型号74LVC4245APW-T的Datasheet PDF文件第7页 
74LVC4245A  
Octal dual supply translating transceiver; 3-state  
Rev. 06 — 18 January 2008  
Product data sheet  
1. General description  
The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting  
3-state bus compatible outputs in both send and receive directions. It is designed to  
interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.  
The device features an output enable input (pin OE) for easy cascading and a  
send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the  
buses are effectively isolated.  
In suspend mode, when VCCA is zero, there will be no current flow from one supply to the  
other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be  
smaller than Vdiode (typical 0.7 V).  
V
CCA VCCB, except in suspend mode.  
2. Features  
I 5 V tolerant inputs/outputs, for interfacing with 5 V logic  
I Wide supply voltage range:  
N 3 V port (VCCB): 1.5 V to 3.6 V  
N 5 V port (VCCA): 1.5 V to 5.5 V  
I CMOS low-power consumption  
I Direct interface with TTL levels  
I Inputs accept voltages up to 5.5 V  
I High-impedance when VCC = 0 V  
I Complies with JEDEC standard no. JESD8B/JESD36  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and 40 °C to +125 °C  
 
 

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