Datasheet > 74LVC4245A-Q100

74LVC4245A-Q100

更新时间： 2024-10-01 01:10:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
17页	830K
描述
Octal dual supply translating transceiver; 3-state

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74LVC4245A-Q100 数据手册

74LVC4245A-Q100

Octal dual supply translating transceiver; 3-state

Rev. 1 — 20 October 2014

Product data sheet

1. General description

The 74LVC4245A-Q100 is an octal dual supply translating transceiver featuring

non-inverting 3-state bus compatible outputs in both send and receive directions. It is

designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply

environment.

The device features an output enable input (pin OE) for easy cascading and a

send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the

buses are effectively isolated.

In suspend mode, when V_CC(A)is zero, there is no current flow from one supply to the

other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be

smaller than V_diode(typical 0.7 V).

V_CC(A) V_CC(B), except in suspend mode.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 5 V tolerant inputs/outputs, for interfacing with 5 V logic

 Wide supply voltage range:

 3 V bus (V_CC(B)): 1.5 V to 3.6 V

 5 V bus (V_CC(A)): 1.5 V to 5.5 V

 CMOS low-power consumption

 Direct interface with TTL levels

 Inputs accept voltages up to 5.5 V

 High-impedance when V_CC(A)= 0 V

 Complies with JEDEC standard no. JESD8B/JESD36

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...17

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