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74LVC1T45GW-Q010 PDF预览

74LVC1T45GW-Q010

更新时间: 2024-01-31 17:59:57
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
29页 216K
描述
IC TRANSCEIVER, Bus Driver/Transceiver

74LVC1T45GW-Q010 技术参数

生命周期:Active零件包装代码:SOT-363
包装说明:PLASTIC, SOT-363, SC-88, 6 PIN针数:6
Reach Compliance Code:unknown风险等级:5.56
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G6
长度:2 mm逻辑集成电路类型:BUS TRANSCEIVER
位数:1功能数量:1
端口数量:2端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):23.5 ns筛选级别:AEC-Q100
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:1.25 mmBase Number Matches:1

74LVC1T45GW-Q010 数据手册

 浏览型号74LVC1T45GW-Q010的Datasheet PDF文件第1页浏览型号74LVC1T45GW-Q010的Datasheet PDF文件第3页浏览型号74LVC1T45GW-Q010的Datasheet PDF文件第4页浏览型号74LVC1T45GW-Q010的Datasheet PDF文件第5页浏览型号74LVC1T45GW-Q010的Datasheet PDF文件第6页浏览型号74LVC1T45GW-Q010的Datasheet PDF文件第7页 
74LVC1T45-Q100; 74LVCH1T45-Q100  
NXP Semiconductors  
Dual supply translating transceiver; 3-state  
Maximum data rates:  
420 Mbps (3.3 V to 5.0 V translation)  
210 Mbps (translate to 3.3 V))  
140 Mbps (translate to 2.5 V)  
75 Mbps (translate to 1.8 V)  
60 Mbps (translate to 1.5 V)  
Suspend mode  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
24 mA output drive (VCC = 3.0 V)  
Inputs accept voltages up to 5.5 V  
Low power consumption: 16 A maximum ICC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC1T45GW-Q010  
74LVCH1T45GW-Q100  
40 C to +125 C  
SC-88  
plastic surface-mounted package; 6 leads  
SOT363  
4. Marking  
Table 2.  
Marking  
Type number  
Marking code[1]  
74LVC1T45GW-Q100  
74LVCH1T45GW-Q100  
V5  
X5  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
5. Functional diagram  
5
DIR  
DIR  
3
A
A
4
B
B
V
V
CC(B)  
CC(A)  
V
CC(A)  
V
CC(B)  
001aag886  
001aag885  
Fig 1. Logic symbol  
Fig 2. Logic diagram  
74LVC_LVCH1T45_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 28 March 2013  
2 of 29  
 
 
 
 

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