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74LVC1G98GV-Q100 PDF预览

74LVC1G98GV-Q100

更新时间: 2024-09-27 11:12:47
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
14页 220K
描述
Low-power configurable multiple function gateProduction

74LVC1G98GV-Q100 数据手册

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74LVC1G98-Q100  
Low-power configurable multiple function gate  
Rev. 1 — 6 December 2022  
Product data sheet  
1. General description  
The 74LVC1G98-Q100 is a configurable multiple function gate with Schmitt-trigger inputs. The  
device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR,  
inverter and buffer; using the 3-bit input. All inputs can be connected to VCC or GND.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices  
as translators in mixed 3.3 V and 5 V environments.  
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it is  
powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power dissipation  
IOFF circuitry provides partial Power-down mode operation  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Latch-up performance exceeds 250 mA  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2000 V  
CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V  
 
 

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