Datasheet > 74LVC1G32GV-Q100H

74LVC1G32GV-Q100H

更新时间： 2024-11-25 20:04:59

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
13页	104K
描述
74LVC1G32-Q100 - Single 2-input OR gate TSOP 5-Pin

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74LVC1G32GV-Q100H 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	TSOP	包装说明：	PLASTIC, SC-74A, SOT-753, 5 PIN
针数：	5	Reach Compliance Code：	compliant
风险等级：	5.77	Base Number Matches：	1

74LVC1G32GV-Q100H 数据手册

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74LVC1G32-Q100

Single 2-input OR gate

Rev. 1 — 7 August 2012

Product data sheet

1. General description

The 74LVC1G32-Q100 provides one 2-input OR function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V applications.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

time.

This device is fully specified for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide supply voltage range from 1.65 V to 5.5 V

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

12 3 4 5 6 7...13

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