5秒后页面跳转
74LVC1G32GM-Q100 PDF预览

74LVC1G32GM-Q100

更新时间: 2024-11-22 11:14:11
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
12页 212K
描述
Single 2-input OR gateProduction

74LVC1G32GM-Q100 数据手册

 浏览型号74LVC1G32GM-Q100的Datasheet PDF文件第2页浏览型号74LVC1G32GM-Q100的Datasheet PDF文件第3页浏览型号74LVC1G32GM-Q100的Datasheet PDF文件第4页浏览型号74LVC1G32GM-Q100的Datasheet PDF文件第5页浏览型号74LVC1G32GM-Q100的Datasheet PDF文件第6页浏览型号74LVC1G32GM-Q100的Datasheet PDF文件第7页 
74LVC1G32-Q100  
Single 2-input OR gate  
Rev. 6 — 18 January 2022  
Product data sheet  
1. General description  
The 74LVC1G32-Q100 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or  
5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V  
environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and  
fall times. This device is fully specified for partial power down applications using IOFF. The IOFF  
circuitry disables the output, preventing the potentially damaging backflow current through the  
device when it is powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 1.65 V to 5.5 V  
Overvoltage tolerant inputs to 5.5 V  
High noise immunity  
CMOS low power dissipation  
IOFF circuitry provides partial Power-down mode operation  
±24 mA output drive (VCC = 3.0 V)  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
Multiple package options  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC1G32GW-Q100 -40 °C to +125 °C  
TSSOP5 plastic thin shrink small outline package; 5 leads;  
body width 1.25 mm  
SOT353-1  
74LVC1G32GV-Q100 -40 °C to +125 °C  
74LVC1G32GM-Q100 -40 °C to +125 °C  
SC-74A  
XSON6  
plastic surface-mounted package; 5 leads  
SOT753  
SOT886  
plastic extremely thin small outline package;  
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm  
 
 
 

与74LVC1G32GM-Q100相关器件

型号 品牌 获取价格 描述 数据表
74LVC1G32GN NEXPERIA

获取价格

Single 2-input OR gateProduction
74LVC1G32GS NEXPERIA

获取价格

Single 2-input OR gateProduction
74LVC1G32GV PANASONIC

获取价格

Single 2-input OR gate
74LVC1G32GV NXP

获取价格

Single 2-input OR gate
74LVC1G32GV NEXPERIA

获取价格

Single 2-input OR gateProduction
74LVC1G32GV,125 NXP

获取价格

74LVC1G32 - Single 2-input OR gate TSOP 5-Pin
74LVC1G32GV-Q100 NEXPERIA

获取价格

Single 2-input OR gateProduction
74LVC1G32GV-Q100,125 NXP

获取价格

OR Gate, LVC/LCX/Z Series, 1-Func, 2-Input, CMOS, PDSO5
74LVC1G32GV-Q100H NXP

获取价格

74LVC1G32-Q100 - Single 2-input OR gate TSOP 5-Pin
74LVC1G32GW NXP

获取价格

Single 2-input OR gate