Datasheet > 74LVC1G17GW-Q100,1

74LVC1G17GW-Q100,1

更新时间： 2024-11-19 08:30:47

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
15页	159K
描述
74LVC1G17-Q100 - Single Schmitt trigger buffer TSSOP 5-Pin

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74LVC1G17GW-Q100,1 数据手册

74LVC1G17-Q100

Single Schmitt trigger buffer

Rev. 1 — 9 July 2012

Product data sheet

1. General description

The 74LVC1G17-Q100 provides a buffer function with Schmitt trigger input. It is capable

of transforming slowly changing input signals into sharply defined outputs.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide supply voltage range from 1.65 V to 5.5 V

 High noise immunity

 Complies with JEDEC standard

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Unlimited rise and fall times

 Inputs accept voltages up to 5 V

 Multiple package options

12 3 4 5 6 7...15

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