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74LV595D,118 PDF预览

74LV595D,118

更新时间: 2024-11-15 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
20页 115K
描述
74LV595 - 8-bit serial-in/serial-out or parallel-out shift register; 3-state SOP 16-Pin

74LV595D,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.29
其他特性:PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT计数方向:RIGHT
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:20000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
传播延迟(tpd):77 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:24 MHz
Base Number Matches:1

74LV595D,118 数据手册

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74LV595  
8-bit serial-in/serial-out or parallel-out shift register; 3-state  
Rev. 03 — 21 April 2009  
Product data sheet  
1. General description  
The 74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs.  
Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS  
device and is pin and functionally compatible with the 74HC595 and 74HCT595.  
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift  
register is transferred to the storage register on a positive-going transition of the STCP  
input. If both clocks are connected together, the shift register will always be one clock  
pulse ahead of the storage register.  
The shift register has a serial input (DS) and a serial output (Q7S) for cascading the  
device. It is also provided with an asynchronous reset input MR (active LOW) for all 8 shift  
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the  
storage register appears at the output whenever the output enable input (OE) is LOW.  
2. Features  
I Optimized for low voltage applications: 1.0 V to 3.6 V  
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 °C  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
I Has a shift register with direct clear  
I Multiple package options  
I Output capability:  
N Parallel outputs; bus driver  
N serial output; standard  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
3. Applications  
I Serial-to-parallel data conversion  
I Remote control holding register  
 
 
 

74LV595D,118 替代型号

型号 品牌 替代类型 描述 数据表
74LV595D,112 NXP

完全替代

74LV595 - 8-bit serial-in/serial-out or parallel-out shift register; 3-state SOP 16-Pin

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