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74LV574PW,112 PDF预览

74LV574PW,112

更新时间: 2024-11-15 15:26:39
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 99K
描述
74LV574 - Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP2 20-Pin

74LV574PW,112 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP2包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.24
其他特性:BROADSIDE VERSION OF 374系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.008 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:25 ns传播延迟(tpd):43 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:4.4 mm
Base Number Matches:1

74LV574PW,112 数据手册

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74LV574  
Octal D-type flip-flop; positive edge-trigger; 3-state  
Rev. 04 — 14 May 2009  
Product data sheet  
1. General description  
The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop  
and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output  
enable (OE) input are common to all flip-flops. It is a low-voltage Si-gate CMOS device  
and is pin and functionally compatible with the 74HC574 and 74HCT574.  
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and  
hold times requirements on the LOW to HIGH CP transition.  
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE  
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the flip-flops.  
2. Features  
I Wide operating voltage: 1.0 V to 5.5 V  
I Optimized for low voltage applications: 1.0 V to 3.6 V  
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 °C  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Common 3-state output enable input  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Ordering information  
Table 1.  
Ordering information  
Package  
Type  
number  
Temperature range Name  
Description  
Version  
74LV574N  
74LV574D  
40 °C to +125 °C  
40 °C to +125 °C  
DIP20  
plastic dual in-line package; 20 leads (300 mil)  
SOT146-1  
SO20  
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1  
74LV574DB 40 °C to +125 °C  
SSOP20  
plastic shrink small outline package; 20 leads;  
body width 5.3 mm  
SOT339-1  
74LV574PW 40 °C to +125 °C  
TSSOP20 plastic thin shrink small outline package; 20 leads;  
body width 4.4 mm  
SOT360-1  
 
 
 

74LV574PW,112 替代型号

型号 品牌 替代类型 描述 数据表
74LV574PW,118 NXP

完全替代

74LV574 - Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP2 20-Pin
74LV574PW NXP

完全替代

Octal D-type flip-flop; positive edge-trigger 3-State
SN74LV574APWG4 TI

功能相似

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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