5秒后页面跳转
74LV574N,112 PDF预览

74LV574N,112

更新时间: 2024-11-15 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
17页 99K
描述
暂无描述

74LV574N,112 数据手册

 浏览型号74LV574N,112的Datasheet PDF文件第2页浏览型号74LV574N,112的Datasheet PDF文件第3页浏览型号74LV574N,112的Datasheet PDF文件第4页浏览型号74LV574N,112的Datasheet PDF文件第5页浏览型号74LV574N,112的Datasheet PDF文件第6页浏览型号74LV574N,112的Datasheet PDF文件第7页 
74LV574  
Octal D-type flip-flop; positive edge-trigger; 3-state  
Rev. 04 — 14 May 2009  
Product data sheet  
1. General description  
The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop  
and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output  
enable (OE) input are common to all flip-flops. It is a low-voltage Si-gate CMOS device  
and is pin and functionally compatible with the 74HC574 and 74HCT574.  
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and  
hold times requirements on the LOW to HIGH CP transition.  
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE  
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the flip-flops.  
2. Features  
I Wide operating voltage: 1.0 V to 5.5 V  
I Optimized for low voltage applications: 1.0 V to 3.6 V  
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 °C  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Common 3-state output enable input  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Ordering information  
Table 1.  
Ordering information  
Package  
Type  
number  
Temperature range Name  
Description  
Version  
74LV574N  
74LV574D  
40 °C to +125 °C  
40 °C to +125 °C  
DIP20  
plastic dual in-line package; 20 leads (300 mil)  
SOT146-1  
SO20  
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1  
74LV574DB 40 °C to +125 °C  
SSOP20  
plastic shrink small outline package; 20 leads;  
body width 5.3 mm  
SOT339-1  
74LV574PW 40 °C to +125 °C  
TSSOP20 plastic thin shrink small outline package; 20 leads;  
body width 4.4 mm  
SOT360-1  
 
 
 

74LV574N,112 替代型号

型号 品牌 替代类型 描述 数据表
74LV574N NXP

完全替代

Octal D-type flip-flop; positive edge-trigger 3-State

与74LV574N,112相关器件

型号 品牌 获取价格 描述 数据表
74LV574PW NXP

获取价格

Octal D-type flip-flop; positive edge-trigger 3-State
74LV574PW,112 NXP

获取价格

74LV574 - Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP2 20-Pin
74LV574PW,118 NXP

获取价格

74LV574 - Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP2 20-Pin
74LV574PWDH NXP

获取价格

Octal D-type flip-flop; positive edge-trigger 3-State
74LV574PWDH-T NXP

获取价格

IC LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, Bus Driver/Transceiver
74LV574PW-T ETC

获取价格

Octal D-Type Flip-Flop
74LV595 NXP

获取价格

8-bit serial-in/serial or parallel-out shift register with output latches 3-State
74LV595A TI

获取价格

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
74LV595D NXP

获取价格

8-bit serial-in/serial or parallel-out shift register with output latches 3-State
74LV595D NEXPERIA

获取价格

8-bit serial-in/serial-out or parallel-out shift register; 3-stateProduction