Datasheet > 74LV175

74LV175

更新时间： 2024-11-11 22:53:19

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
8页	156K
描述
QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74LV175 数据手册

SN54LV175A, SN74LV175A

QUADRUPLE D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS400B – APRIL 1998 – REVISED OCTOBER 1998

SN54LV175A . . . J OR W PACKAGE

SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Process

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

CLR

Typical V

> 2 V at V

(Output V

Undershoot)

CLK

OHV

= 3.3 V, T = 25°C

Contain Four Flip-Flops With Double-Rail

Outputs

Applications Include:

– Buffer/Storage Registers

– Shift Registers

GND

– Pattern Generators

Latch-Up Performance Exceeds 250 mA Per

JESD 17

SN54LV175A . . . FK PACKAGE

(TOP VIEW)

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

2 1 20 19

18 4Q

Package Options Include Plastic

Small-Outline (D, NS), Shrink Small-Outline

(DB), Thin Very Small-Outline (DGV), and

Thin Shrink Small-Outline (PW) Packages,

Ceramic Flat (W) Packages, Chip Carriers

(FK), and DIPs (J)

9 10 11 12 13

description

NC – No internal connection

The ’LV175A devices are quadruple D-type

flip-flops designed for 2-V to 5.5-V V operation.

These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the

positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

The SN54LV175A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74LV175A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

CLR

CLK

↑

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7 8

中文翻译

下载PDF

与74LV175相关器件

型号	品牌	获取价格	描述	数据表
74LV175D	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LV175DB	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LV175DB-T	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LV175D-T	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LV175N	ETC	获取价格	Quad D-Type Flip-Flop
74LV175PW	ETC	获取价格	Quad D-Type Flip-Flop
74LV175PWDH	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LV175PWDH-T	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LV175PW-T	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LV17A	NEXPERIA	获取价格	Hex buffer Schmitt trigger

与74LV175相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

8
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

9
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

32

产品中心

服务支持

精选活动

关于我们

帮助中心

74LV175

74LV175 数据手册

与74LV175相关器件

与74LV175相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74LV175

74LV175 数据手册

与74LV175相关器件

与74LV175相关文章

您还可以找

您在本页遇到什么问题？