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74LS243 PDF预览

74LS243

更新时间: 2024-11-17 22:53:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器
页数 文件大小 规格书
5页 56K
描述
Quadruple Bus Transceiver

74LS243 数据手册

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August 1986  
Revised January 2000  
DM74LS243  
Quadruple Bus Transceiver  
General Description  
This four data line transceiver is designed for asynchro-  
nous two-way communications between data buses. It can  
be used to drive terminated lines down to 133.  
Features  
Two-way asynchronous communication between data  
buses  
PNP inputs reduce DC loading on bus line  
Hysteresis at data inputs improves noise margin  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS243M  
DM74LS243N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Control  
Inputs  
Data Port  
Status  
G AB  
GBA  
A
B
H
L
H
H
L
O
I
(Note 1)  
I
(Note 1)  
H
L
ISOLATED  
L
O
I = Input  
O = Output  
H = HIGH Logic Level  
L = LOW Logic Level  
Note 1: Possibly destructive oscillation may occur if the transceivers are  
enabled in both directions at once.  
© 2000 Fairchild Semiconductor Corporation  
DS006412  
www.fairchildsemi.com  

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