74LS245PCQR

更新时间： 2024-11-18 13:04:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
6页	70K
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数据手册

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74LS245PCQR 数据手册

August 1986

Revised March 2000

DM74LS245

3-STATE Octal Bus Transceiver

General Description

Features

These octal bus transceivers are designed for asynchro-

nous two-way communication between data buses. The

control function implementation minimizes external timing

requirements.

■ Bi-Directional bus transceiver in a high-density 20-pin

package

■ 3-STATE outputs drive bus lines directly

■ PNP inputs reduce DC loading on bus lines

■ Hysteresis at bus inputs improve noise margins

■ Typical propagation delay times, port-to-port 8 ns

■ Typical enable/disable times 17 ns

The device allows data transmission from the A Bus to the

B Bus or from the B Bus to the A Bus depending upon the

logic level at the direction control (DIR) input. The enable

input (G) can be used to disable the device so that the

buses are effectively isolated.

■ I_OL(sink current)

24 mA

■ I_OH(source current)

−15 mA

Ordering Code:

Order Number Package Number

Package Description

DM74LS245WM

DM74LS245SJ

DM74LS245N

M20B

M20D

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Enable

Direction

Operation

Control

DIR

B Data to A Bus

A Data to B Bus

Isolation

H = HIGH Level

L = LOW Level

X = Irrelevant

DS006413

www.fairchildsemi.com

12 3 4 5 6

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