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74LCX16245MTD_NL PDF预览

74LCX16245MTD_NL

更新时间: 2024-11-04 21:17:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 输入元件光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 119K
描述
Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 6.10 MM, LEAD FREE, MO-153, TSSOP-48

74LCX16245MTD_NL 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:48
Reach Compliance Code:unknown风险等级:5.67
其他特性:5V TOLERANT INPUTS AND OUTPUTS系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:12.5 mm逻辑集成电路类型:BUS TRANSCEIVER
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):5.4 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:6.1 mm
Base Number Matches:1

74LCX16245MTD_NL 数据手册

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February 1994  
Revised May 2005  
74LCX16245  
Low Voltage 16-Bit Bidirectional Transceiver  
with 5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX16245 contains sixteen non-inverting bidirectional  
buffers with 3-STATE outputs and is intended for bus ori-  
ented applications. The device is designed for low voltage  
(2.5V or 3.3V) VCC applications with capability of interfac-  
2.3V–3.6V VCC specifications provided  
4.5 ns tPD max (VCC 3.3V), 20 A ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
ing to a 5V signal environment. The device is byte con-  
trolled. Each byte has separate control inputs which could  
be shorted together for full 16-bit operation. The T/R inputs  
determine the direction of data flow through the device.  
The OE inputs disable both the A and B ports by placing  
them in a high impedance state.  
24 mA output drive (VCC 3.0V)  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LCX16245 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model 2000V  
Machine model 200V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V  
through a pull-up resistor: the minimum value or the  
CC  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX16245G  
(Note 2)(Note 3)  
BGA54A  
MS48A  
MTD48  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LCX16245MEA  
(Note 3)  
74LCX16245MTD  
(Note 3)  
Note 2: Ordering code Gindicates Trays.  
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS012001  
www.fairchildsemi.com  

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